Toshiba's Paper Thin Package Formed by Wafer Bumping
|David Francis and Linda Jardine
PATENT NUMBER: 6,239,496
INVENTOR: Junichi Asada
TITLE: Packaging Having a Very Thin Semiconductor Chip, Multichip Module Assembled by the Package, and Method for Manufacturing the Same
In an earlier approach, individual chips were TAB bonded, encapsulated and then stacked on one another. Each successive device required longer TAB leads with bonding sites either extending beyond the first one or placed on top of one another. The result was increased height and board area for each added device.
This stacked module is more like a multi-package module than a multichip one.
Toshiba refers to this patent as a "Paper Thin Package" (PTP). The thickness of this package (5.1 mils) is slightly thicker than copy paper (4 mils), but thinner than business card stock (8 mils).
The individual packages are assembled as shown in the accompanying figure.
The first step in the process is wafer bumping, with conventional gold ball bonding employed to form bumps on the wafer.
The next step is to thin the wafer to 50 microns (2 mils). Dicing before grinding (DBG), is the method used. In DBG, the wafers are sawn part way through. The sawn depth is required to be deeper than the final die thickness, which enables the wafer to be handled and taped without yield loss. (The wafers used in this memory application are 300 mm in diameter.)
The taped wafer is then placed on a grinding machine, where it is thinned to 50 microns (2 mils). As the grinding wheel approaches the final thickness, the saw lines are exposed, and the wafer is automatically diced. After cleaning and drying, the die are attached to the substrates.
The substrates are fabricated using conventional flex or TAB processing. An anisotropically conductive adhesive (ACA) is applied to the substrate and the die flip-chip bonded into position. The ACA also acts as an encapsulant for the chip.
The flex features copper on one side only, with through-holes formed in the polyimide where vertical connections are to be made.
The insert figure shows how individual packages are stacked to form a completed module. Solder is used to connect the packages.
Copper patterns on the surface of the substrates act as stiffeners. There are no leads and no copper in the exact center of the film, with the result that the package is easily flexed and broken at this point. To minimize this problem, the packages in the stack are offset so that this weak spot does not occur at the same point for all packages.
Toshiba paper thin memory stack
The idea described in this patent allows multiple packaged die to be stacked four high to a height that is roughly equivalent to the newest standard package height of 0.5 mm (20 mils).
Toshiba is using this process to stack four (4) flash memory devices on a smart media card. A 1 Gbit smart media card employs four 256 Mbit flash die.
As silicon is thinned down to 50 microns and below, it becomes more flexible, which allows it to be used in a variety of new applications. One application area is the new family of thinner smart cards that are one-third the thickness of the previous version.
Another interesting application is as a postage-like stamp with a wireless antenna that can be pasted to any surface. It can also be used as an RFID tag.
There is growing interest in thinning silicon for these new applications and for stacking die in standard packages.
International Interconnection Intelligence is a market and technology research company specializing in the semiconductor packaging and interconnection areas. Contact David Francis or Linda Jardine by e-mail at email@example.com or by phone at 650.728.5270. [iii1.com]