Keeping Pace with Technology Demands Changes in Package Design and Selection

Semiconductor makers and packaging engineers are confronting a new set of challenges as ICs become faster, smaller and more power hungry. Keeping pace with the latest technology advances demands implementing massive changes in package design and routing practices. Electrical and thermal test methods must also be re-examined, since standard tests may no longer apply.

Figure 1. ASAT's new LPCC (Leadless Plastic Chip Carrier)

New surface mounted package types have become popular for a number of reasons, not the least of which is their ability to pack more I/O into given area than older formats. Additionally, since they tend to operate at extremely high speeds, these packages must exhibit lower parasitics.

Today's evolving, high-density packages typically fall into the following categories:

• Fine-pitch ball grid arrays (FBGA), which are housed in extremely small CSPs. Packages utilizing flexible substrates are the smallest, while rigid-substrate packages are slightly larger.
• Leadless plastic chip carriers (LPCC), which are leadframe-based packages (chip-size packages typically used for lower pin counts)
• Thermally enhanced packages, which may include:
• 1. The leadless plastic chip carrier (LPCC)
• 2. The exposed pad package (EPP) (for example, TQFP, SOIC)
• 3. The tape ball grid array (TBGA)

Compare a 27-mm FBGA, for example, with its equivalent leaded plastic package. While the FBGA can provide 672 I/Os, its equivalent leaded part offers only about 200 I/Os. Moreover, the FBGA conserves valuable motherboard space, due to its small size. Additionally, because they are so thin, fine-pitch packages are useful for handheld and other portable devices, games and PCMCIA cards.

Perhaps the most important benefits of today's high-density packages are improved electrical and thermal characteristics. These parameters are often dramatically improved with an advanced package type.

Here's how that works: Use of an FBGA, as opposed to a larger plastic BGA, yields significant density improvements, because the FBGA typically needs less than half the amount of board real estate required by the PBGA. Because the FBGA is so much smaller, electrical parasitics decrease at about the same rate, with both inductance and capacitance slashed to half the number expected with a plastic BGA. With reduced parasitics, the board becomes capable of running much faster.

The desirable features of high-density, fine-pitch packages are not without tradeoffs. As the devices become smaller and smaller, they also become exceedingly more difficult to design, route and test.

Therefore, device manufacturers and packaging engineers must start asking the following questions for each new semiconductor design:

• How must the package be designed?
• What is the most effective way to test it?
• What performance improvements can be expected?

Another consideration in package selection concerns flexible substrates. While flexible substrates offer the highest densities and smallest sizes, they typically do not provide the same board-level reliability results as rigid substrates.To achieve success working at these densities, chip manufacturers must be prepared to invest in a far more complex design as well as a highly sophisticated means of modeling both thermal and electrical parameters.

A new package design, ASAT's proprietary LPCC (Figure 1), is a leadframe-based package typically able to accommodate up to a 50 percent reduction in package size compared to standard plastic leaded packages. Several options are available on the market. Those with exposed die-attach pads offer dramatic improvements in thermal and electrical characteristics, because the exposed pads can be used as a ground plane as well as a heat sink.

The LPCC offers the potential of becoming the most cost-effective package for high-speed, high-frequency applications in lower-pin-count packages. The demand for this package type is increasing at a tremendous rate, and the packages themselves will be a registered JEDEC standard within the next year.

Because of the LPCC's unique construction, however, standard test methods are extremely difficult to apply. The die-attach pad is typically soldered to the printed circuit board, and since the electrical measurements are referenced to a ground plane, accurate capacitance measurements are difficult to obtain. Since standard electrical test measurement techniques cannot be used, new ones must be developed (See Figure 2 for a comparison of the LPCC's electrical parasitics vs. other packages).

Furthermore, the LPCC requires a dramatic change in the relative importance of standard measurements. For example, ® Ja (junction-to-ambient-air temperature) is difficult to measure, because the package is soldered directly to the board. Instead, the ® Jb (junction-to-board) measurement now becomes one of the most significant characteristics to examine.

Until now, however,this measurement has rarely been used, so many packaging engineers are not familiar with it. In light of the growing popularity of LPCCs, another required measurement is ® Jc (junction-to-case). Clearly, there will be a learning curve involved in getting many engineers to the point where they feel comfortable using new methods to examine and assess these advanced packages.

The EPP is a standard leaded package, but just as with the LPCC, the exposed pad can be soldered down. So again, the ® Jc and ® Jb become very pertinent test measurements. Likewise, engineers working with the EPP will encounter thermal issues that are similar to the LPCC package.

The TBGA is arguably the highest-performing plastic package available. However, since it is typically used in very high performance applications, it is vital to obtain accurate readings in all three key areas: ® Ja, ® Jb and ® Jc. This requires specialized design software and test tools in order to obtain precise, predictable, manufacturing-process variables. Given today's tooling costs and time-to-market pressure, new designs must work the first time out.

The TBGA is offered with both single- and two-layer tapes, giving designers the flexibility to add the advantages of options, including controlled impedance, matched impedance and minimized ground-bounce shielding.

In addition, the TBGA is a preferred package choice because its structure allows multiple ground planes, multiple power planes, multiple bond rings and optimized signal routing. Thus the materials typically used in TBGAs generate the lowest possible parasitics of any plastic package.

The highly attractive benefits this package offers pose significant manufacturing challenges. Modeling is difficult with the TBGA, so highly sophisticated modeling tools must be used. Particularly for thermal modeling, complex software tools are required. Of course, skilled modeling expertise is a prerequisite for using these advanced tool sets.

To further compound the difficulty in modeling the TBGA, familiar electrical measurements may not apply to it. In fact, the use of standard JEDEC test setups may yield erroneous readings.

So once again, standardized test methods must now adapt to the times.

Figure 2. Electrical Parasitic Comparison of LPCC Vs. QFP, TQFP and fpBGA

IC manufacturers that want to take advantage of the new paradigm in packaging, must be prepared to confront the accompanying challenges. This paradigm requires a substantial investment in new design software and test tools and a major revamping of test methodologies and processes.

In support of these changes, semiconductor companies will have to recruit experienced packaging engineers and develop skilled design and test organizations. Companies not prepared to make substantial commitments should consider partnering with a trusted subcontractor possessing the skills and capabilities necessary to ensure success.