November- December 1998
eMail the Editor
Reliability Issues Take Center StageDear Reader:
The relentless pressure to miniaturize ICs is creating a demanding set of issues for the packaging engineer. As the package is scaled down to the size of the chip, large thermal expansion mismatches must be accommodated across very small dimensions, raising important reliability issues.
A major function of the package is to connect the silicon world with an expansion coefficient of 3 ppm/°C to the copper-based circuit board with its expansion of 17 ppm/°C. Bridging the gap from silicon to copper is one of the most challenging aspects of designing chip-scale packages today.
Conventional packaging solved the expansion mismatch problem simply by using long, flexible leads to connect the device to the circuit board, where leads on through-hole packages served to isolate the device from thermal and mechanical shocks.
As the package thickness diminished in SOPs, TQFPs and TSOPs, flexure of the leads became an increasingly important consideration. With the advent of CSPs, the electrical connections have been further reduced in size, making them the single most important factor in system reliability.
Reliability issues become acute as CSPs move into applications requiring larger chips, higher power and higher performance. Currently, the primary measure of reliability is temperature cycle failure, although other factors are receiving increasing attention. Power cycling in high-performance processors, particularly those with power-saving features, generates thermal transients and related mechanical stresses.
Werner Engelmaier presents the expert's view of the substrate challenges ahead in his interview with Editorial Director Joseph Fjelstad.
The articles chosen for this edition represent a sophisticated array of the engineering disciplines now being applied to CSPs. Finite element modeling is becoming increasingly important in understanding the causal factors of failure, which often involve non-linear and visco-elastic phenomena. Modeling and materials science are guiding the design of CSPs along several competing paths.
The growing level of scientific analysis in reliability studies is an indicator that chip-scale packaging is beginning to mature from its infancy as it moves into the mainstream of electronics.
Dr. Tom Di Stefano
Chip Scale Review o 7291 Coronado Drive, Suite 8 o San Jose, CA 95129 o Email: email@example.com
|© 1998 ChipScale REVIEW|