November- December 1998
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Chip-Scale Package Assembly Reliability
Although the weakest link of CSP assembly reliability is often internal package failure, solder-joint fatigue is still considered the key reliability factor.-By Dr. Reza Ghaffarian, Jet Propulsion Laboratory, California Institute of Technology, Pasadena, Calif.
While many factors affect solder-joint reliability, including package type, package build, board design and assembly variables, solder-joint fatigue is the leading cause of failure today.
There are several surface mount package styles, both active and passive. Active devices are divided into those with leads terminating on the periphery of the component (two or four sides) and those with terminations (either pads or solder bumps) over much of the bottom of the component. Peripheral-array packages carry a smaller potential for significant size reduction with increased I/O counts than do area array packages.
The ball grid array format, an area-array package, is now the main alternative to the peripheral-array format. For example, the CSP version of the two-sided peripheral-array package is the lead-on-chip (LOC) package. The area-array versions of the LOC package are micro-type or mini-type, fine pitch BGA packages, generally with eutectic solder balls.
Chip-scale packages combine the benefits of small size and performance with the advantages of standard die packages. While a CSP is generally defined as a package that is no larger than 1.2x the perimeter or the area of the die, many manufacturers refer to CSPs when the package is a miniature version of the previous generation.
Solder performs both electrical and mechanical functions in surface-mount electronics. Thus, damage to solder may readily affect a system's functional integrity. Therefore, identifying defects that cause changes either in mechanical or electrical system characteristics, and discovering why they fail, are critical. The most common solder-joint damage is induced by thermal cycling. The main cause of this damage is generally a result of the differences between the thermal expansion of package and PWB materials. This is especially true for eutectic solder (63Sn/37Pb), which creeps at room temperature.
Creep for materials usually occurs at levels above half of the absolute melting temperature (T/Tm >0.5), which represents a value of 0.65 at room temperature for eutectic solder.
Thermal cycling damage, usually caused by creep and stress relaxation, is expected to increase even more with the trend toward energy conservation.
Powering down whenever a system is not actively used results in more cycles. Previously, electronic hardware was usually left on for long periods of time, resulting in relatively few thermal cycles. The on-off demand raises more concerns regarding solder joints which are affected by thermal cycling.
Thermal damage to solder joints is most often caused by:
A global CTE mismatch between the package and the board which induces stresses. The package and board can also display temperature gradients through the thickness and at surface areas.
A local CTE mismatch between the solder attachment to the component and the PWB.
Reducing the CTE mismatch of components and PWBs reduces cycling damage. The ideal conditions, however, depend on the thermal conditions of the component, PWB and solder. An ideal CTE-matched condition is a tailored PWB material with a slightly higher CTE value than the component. This is based on the assumption that the global CTE mismatch is dominant, and that the component with the heat-generating die is hotter than the PWB.
There are other approaches to reducing damage to solder joints. The application of underfill is a common technique, and one that has been widely used for direct attachment of chip-on-board or when package leads are not robust. Other less-conventional approaches are aimed at absorbing the CTE mismatch between the die and board within the packageor externally through strainabsorbing mechanisms, which reduce stress on the solder interconnects. These approaches can, however, introduce their own unique damage since the weakest link will be transferred from solder to other areas of the attachment system.
Thermal cycling and a series of other environmental tests are commonly used to gain confidence in the reliability of surface-mounted packages and assemblies. There are additional tests tailored to specific applications.
For aerospace applications, the vibration and shock representative of a launch is an example of a tailored experiment. For portable products, new tests are being carried out. Bend, drop and, perhaps, washing machine-type tests are especially important. It is interesting to note that these tests are devised to meet the harsh environments generated by human mishandling. Customer perception of quality and reliability of products might become a reality, even though these tests may not have any scientific basis.
CSP Thermal Cycling Data
Tables 1-3 show thermal cycles to failure under different conditions for various CSPs with low to high I/Os. Except for the Tessera BGA package, most other test results shown are from package manufacturers. Although manufacturer-supplied data is valuable, because it has probably been generated for selected packages under extreme control, it might not represent user-application environments.
In Table 1, where BGA package results are given, two users showed 1,000 and 500 failure cycles in the range of -55°C to 125°C. The higher value is possibly from a more controlled environment, while the lower value may represent a mix of different supplier licensees for this package.
Among the grid array packages, the JACS-Pak is the only format which shows higher than 1,000 cycles to failure in the same temperature range. Ceramic CSPs show much closer reliability to this than their surface-mounted versions. The reasons may include size and thickness reduction. Strain induced on the ceramic joint is directly related to size or distance to neutral point (DNP). Note again that these data were generated by suppliers and no independent validation tests are available.
Wafer-level assemblies often show very few cycles to failure, and most of them require underfilling to achieve reliability comparable to conventional mounted packages. Leaded CSPs with low I/O generally exhibit reliability comparable to their surface-mounted counterparts (Table 3). There is a great difference between the two independent sets of data for TSOPs (thin small outline packages). The two extremes are 200 and 2,200 failure cycles in the range of -55°C to l25°C.
A recent assembly characterization by a user revealed much valuable information.1 Most packages failed early and did not meet the user requirement for cycles to failure. Only two out of eight packages from six manufacturers passed the user failure-free cycles requirement.
Acceptable failure-free cycles were 3,500 cycles for thermal cycling in th range of 0°C to 100°C. The results were at least an order of magnitude low than those for plastic BGA packages. Failures lower than 1,000 cycles, even in the range 0°C of 100°C, are a good indication of package immaturity at the time of evaluation (late 1997).
It is difficult to determine if the underfill might have relieved these early failures, since no information by package manufacturers is available. While detailed failure mechanism analyzes might have revealed that the use of underfill would reduce the number of failures, underfilling was considered unacceptable because of additional assembly steps.
There are many other factors that affect CSP reliability. These include design, package build, solder paste, assembly underfill and type of test for reliability evaluation. A few of these variables are discussed below:
PWB pad design: For BGAs, discussions on the use of solder-mask defined non-solder mask (SMD vs. NSMD) were hot subjects for a short period. There were two camps: One claimed improvement from the use of SMD. This group reasoned that masks over copper were needed for improved adhesion. They also believed that the potential benefits of cycles to failure increased due to increased solder joint height. The other camp showed that crack initiation in solder, due to overlaying of the mask, could reduce the number of cycles to failure. NSMD is now commonly recommended.
The pad-size design relative to package has its own supporters. As a rule of thumb, the board pad size should be the same as the package. A slight imbalance in this relationship could result in a failure at the board or package level. Optimized conditions might differ for different packages depending on the ball attachment configuration.
Die bond on interposer: There are various techniques employed to transfer the die I/O to the interposer within the package. Each element of the package's internal form has its own effect. For TAB-bonded CSPs, the bond is the weakest link.
For flip-chip die in the JACS-Pak, the failure was observed on the C5 (board level) solder joint interconnection when subjected to thermal cycling. This might not be the general case for the flip-chip die. CSPs and BGAs with flip-chip dies are more susceptible to internal package failure than their wire-bonded versions, however.
Interposer thickness: When the interposer was increased from 0.4 mm thickness to 0.6 mm, cycles to failure increased from 400 to about 800 cycles (-25°C/125°C). Data for JACS-Pak indicates that a semi-rigid interposer would have 1.88x the number of thermal cycles. Is the rigidity equivalent to the thickness change or was the rigidity affected because of a materials change? The answer is not known. The interposer CTE also significantly affects board reliability.
Interposer materials: CSPs with different interposer materials showed significantly different cycles to failureŃ representing about a 3x increase.2 An experiment found that a factor of about 3x will be achieved when a low-CTE interposer was used (1200 vs. 400 cycles, -25°C/125°C).
Die size: A study conducted by Amkor Electronics3 shows that when die size increased from 6.4 mm to 9.5 mm, the first cycles to failure decreased from 1500 to 900 cycles in the range of -40°C to 125°C.
Solder composition: Eutectic solder (63/37) is the most commonly used solder due to its many desirable attributes, including a low temperature melting point. To improve fatigue characteristics, small amounts of silver (2%) have been added to this composition. Additive materials potentially may form brittle intermetallic phases and may become soft, as well, through forming precipitates. These metallurgical transitions are further accelerated by increases in temperature. The effects of a five-element alloy improved thermal cycling reliability by 1.2x-1.5x according to another study.4
Ball shape attachment: It has been demonstrated that the DBGAs (Dimple BGA) improves reliability. This might be the case for CSPs too, but the importance of ball shape to reliability is yet to be demonstrated.
Solder joint height: The effect of solder joint height on reliability has been widely discussed for BGAs. One reason for the use of an SMD pad for PBGAs with collapsible solder was to increase solder ball height and thereby increase reliability.
Height was also increased by the use of columns in ceramic column grid array packages. These CGAs achieved significant reliability improvements over the ball grid array versions. Improvement was shown for CSPs when ball heights were increase.2 When solder height was doubled, cycles to failure for the board tripled.
Underfill: One key advantage of CSPs over flip chips is that, ideally, there is no requirement for CSPs to be underfilled. The assemblers for consumer products prefer packages with no underfill, since one process step is eliminated and reworkability is permitted. However, for high reliability applications, where vibration and shock are key factors in ruggedness, the use of underfill might be the only solution now known to meet these requirements.
Flip chips with very short cycles to failure have shown that underfill will improve cycles-to-failure reliability by an order of magnitude (5-10 at least). This is very similar to the results shown in Table 2 for the wafer-level miniBGA packages with and without underfill.
Double Reflow: There are many concerns in the assembly of double-sided boards. Reliability reduction is one. For heavy BGAs, one concern was potential parts fall from the assembled side during the second reflow. There may be similar concerns for CSPs with the small solder volume which does not provide enough tension force to hold even the smaller sized CSPs.
Additionally, studies show that for two-sided packages, the reliability of board assembly is half of the single-sided packages.2 Recently, similar test results were presented for another CSP package.5 Double-sided assemblies with packages on directly opposite sides of the board showed lower cycles to failure. These numbers were improved with partial relative package offsets on both sides.
Solder joint interconnects are considered to be the main cause of assembly failure. Failure at the board level can also be caused by the internal failure of the package. For example, package internal TAB-lead failures at heels were reported for the CTE-absorbed CSPa fatigue failure shift from the solder joint to the internal package (see Table 1).
This new type of failure is in contrast to the traditional, theoretical wisdom where solder joint failure is generally considered to be the weak link in solder joint assemblies. This and other failure mechanisms, which are now being established for CSPs, must be understood by a modeler to predict a meaningful reliability projection.
Table 4 includes four projections from different modelers with test results. It is interesting to compare the theoretical values with experimental test results for numerous CSPs. It becomes obvious that these calculations are at least 5-20x higher than the test results. As noted, the highest value test results are in the range of 1,000-1,500 cycles. Projections of more than 20,000 cycles to failure in the range of -55°C to 125°C are far beyond the imagination; and are misleading.
Similarly misleading results may also occur when DNP is used as the indicator for cycles to failure. In the IPC report JSTD-012 (Joint Industry Standard implementation of Flip Chip and Chip Scale Technology), assembly reliability projections were based on flip-chip die being attached to the board.
DNPs were used to calculate the first failure and for projecting failure with the size of the package. This is not valid for most CSPs, except possibly for a few wafer-level packages without underfill.
Although there is a relationship between an increase in die size and reliability, the relationship is not linear and depends on many parameters. For example, fan-out packages with small die will not follow the DNP indications.
Lessons Learned and Recommendations
Board reliability information is essential CSP implementation for high reliability applications. This information will also facilitate the use of CSPs in the commercial sector. For wider application of this technology, the potential user will need design reliability data, since users often do not have the resources, time or ability to perform complex environmental characterizations.
To help build the infrastructure in these areas, nearly 300 test vehicles were assembled by the JPL-led consortium to address many technical issues regarding the interplay of package types, I/O counts, PWB materials, surface finishes and manufacturing variables for the quality and reliability of assembly packages. The following conclusions are based on the data analysis and comparison in the literature:
Board reliability information is essential for CSP implementation for high reliability applications.
The research described in this article is being carried out by the Jet Propulsion Laboratory, California Institute of Technology, under a contract with NASA.
Dr. Ghaffarian received his Ph.D. in engineering from the University of California, Los Angeles. He currently supports R&D activities at the Jet Propulsion Laboratory for BGAs, CSPs and surface mount technology. Dr. Ghaffarian's paper, "Joint Integrity of Chip-Scale Packages under Isothermal Aging," appeared in our July issue. Readers may contact him at firstname.lastname@example.org, by phone at 818.354.2059 orfax 818.393.5245.
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