November- December 1998
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Table 3. CSP Assembly Reliability (Lead-on-Chip)
|
Package Schematic (not to scale) |
Package Type |
Cycling Condition |
Total Cycles |
Fails/Samples | I/O | References |
|
LOC-USON (fujitsu) LOC ultra-thin small outline no-lead |
-65°C 30 min. to 150°C, 30 min. | 500 | 0/40 | 26 | J. Kasai, et al, "Low Cost Chip Scale Package for Memory Products," Surface Mount International, August 29-31, 1995 |
|
LOC (BLP) LGSemicon TSOP |
-30°C 85°C -55°C to 125°C Shock, 5 min. dwells -55°C to 125°C Shock, 5 min. dwells |
>1200 800 900 900 1000 |
N/A 0/4 2/4 0/25 2/25 |
20 28 28 |
Y. Kim, et al, "Bottom Leader Plastic (BLP) Package: A New Design with Enhanced Solder Joint Reliability," Proceeding of IEEE Electronic Components & Technology Conference, May 1996, P. 448-452 Y. Kim, et al, "Solder Joint Reliability of The Leaded and Leadless Packages: New BLP Design," SEMICON West, July 18-12, 1997, Austin, Texas |
|
Hitachi Cable LOC | -50°C to 150°C 30 min., 10 min between | >1000 | No Crack | 44 | K. Hatano, at al, "Reliability of CSP Manufactured by Using LOC Package Technology," IMAPS ATW Workshop on CSP, August 10-12, 1997, Austin, Texas |
|
TSOP |
-55°C to 125°C -55°C to 125°C 0°C to 100°C 0°C to 100°C |
2,200 200 735 750 |
1st Failure 1st Failure 1st Failure 1st Failure |
32 32 32 32 |
J. Lau, editor, "Solder Joint Reliability Theory and Applications R. Darveau P. Viswanadham, et al, "Solder Joint Reliability on TSOPs-An Overview", IEEE 43rd ECTC, P 883, 1993 D. Noctor, et al, IEEE Trans on CHMT, Vol. 16, No.6, 1993 |