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May • June 2019; Volume 23, Number 3

Cover Photo

Automotive applications are driving a number of packaging technologies, such as reliability of packaging materials and screening of SoCs. But flexible hybrid electronics (e.g., for biosensors and personal wearable body monitors) and “More than Moore” nontraditional scaling are also pushing the packaging market segment forward. This issue covers the above topics in detail across a broad swath of the packaging industry.


Cover image courtesy of Brewer Science, Inc.

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White Paper: System-level, post-layout electrical analysis for high-density advanced packaging
As HDAP designs become more popular, the need for post-layout simulation (analog) and post-layout STA (digital) flows to augment basic physical verification (DRC and LVS) is growing. Mentor provides an accurate, automated flow that generates the required HDAP netlist for simulation/STA to enable HDAP designers to ensure that the HDAP will perform as designed.
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Industry News

June 2019

Purdue and TSMC, the world’s largest semiconductor manufacturer, collaborate to research secured microelectronics ecosystem

West Lafayette, IN – June 14, 2019 - Purdue University and the Taiwan Semiconductor Manufacturing Co. (TSMC) jointly announced plans Friday to establish a Center for Secured Microelectronics Ecosystem aimed at ensuring a secure supply of semiconductor chips and related tools all the way from the foundry to the packaged system.

TSMC, located in Hsinchu Science Park, Taiwan, is the world’s largest semiconductor contract manufacturer, and Purdue University officials reached an agreement in Washington, D.C., during the Select USA Conference.

The center, to be located at the Purdue University West Lafayette campus in collaboration with Purdue Research Foundation, will perform research to ensure a secure ecosystem for the manufacture of microelectronics systems.

“Semiconductors will continue to be the enabling backbone for technological and economic growth in the 21st century, propelling advancements in the internet of things, autonomous transportation, artificial intelligence, advanced manufacturing, and many other applications,” U.S. Secretary of Commerce Wilbur Ross said. “We are pleased that TSMC and Purdue University took their partnership to the next level at SelectUSA — a platform for leading global semiconductor manufacturers to continue expanding and investing in the United States. Under President Trump’s leadership, the administration will continue doing all it can to grow and equip our highly skilled workforce, maintain our competitive investment and regulatory environment, and support world-class American research universities.”

Purdue University is ranked 12th among worldwide universities granted U.S. utility patents for 2018 in the annual rankings put out by the National Academy of Inventors and the Intellectual Property Owners Association.

“This agreement solidifies a vital global partnership for Purdue and enables our leading researchers to further advance their discoveries in microelectronics,” Purdue University President Mitch Daniels said. “TSMC’s commitment is only the beginning of what we believe will be an internationally significant initiative.”

The Purdue School of Electrical and Computer Engineering has about 10 faculty members currently collaborating with TSMC at various levels of research.

“TSMC is pleased to have this opportunity to support Purdue’s world-class technology research,” said H.S. Philip Wong, vice president of corporate research at TSMC. “As everyone’s trusted foundry, TSMC believes it would be beneficial to contribute to the development of a secure electronics ecosystem.”

The Purdue School of Electrical and Computer Engineering will lead the research and development in conjunction with TSMC.

“We are truly excited about this opportunity to significantly broaden and deepen the important partnership with TSMC. We anticipate the new center will begin operations at the beginning of the new academic year. At the start, we will focus on developing a secure microelectronics ecosystem,” said Mung Chiang, Purdue’s John A. Edwardson Dean of the Purdue College of Engineering. “We also anticipate that the partnership will grow in the next couple of years to include multiple U.S. universities.”

In February, the Semiconductor Industry Association reported that the global semiconductor industry posted sales of $468.8 billion in 2018, the industry’s highest-ever annual total, and an increase of 13.7 percent compared with the previous year.

“This industry is one of the most important for our global economy and security,” said Chad Pittman, vice president of the Purdue Research Foundation National Security and Defense Program Office and Government Relations. “The strengths in research and development of Purdue and TSMC will help support and advance this critical industry on multiple levels and help secure the ever-advancing microelectronics technology.”

The agreement also allows TSMC to help facilitate access to multi-project wafer shuttle runs to test the effectiveness of the proposed research and to assign representatives on the advisory board of the center to mentor specific projects.

For additional information:

Mung Chiang, 765-494-5346,
Chad Pittman,
Elizabeth Sun,

In Memoriam
Wayne K. Pfaff
1935 ~ 2019

Irving TX - June 17, 2019 - Wayne Pfaff, the founder of Plastronics Socket Company, passed away peacefully on Thursday, June 13 surrounded by his family. Wayne was born on August 2, 1935, in Salinas, California. Wayne, an engineer with a brilliantly creative mind started Plastronics in 1983 with the intent of serving the semiconductor industry with smart solutions to tough problems. The company Wayne started has over 25 patents, which includes the zero-insertion force (ZIF) open top socket used globally across all test socket companies. It is Wayne’s inventions that form the foundation of the burn-in test socket industry we know today. Wayne Pfaff will forever be remembered as an industry leader and innovator and his legacy will continue to live on with David Pfaff, President of Plastronics, and the entire Plastronics team.

Plastronics Socket Company, 2601 Texas Drive, Irving, Texas 75062 - 972-342-1834

April 2019

A*STAR and Soitec launched a joint program to develop a new layer transfer process for advanced packaging

The Agency for Science, Technology and Research’s (A*STAR) Institute of Microelectronics (IME) and Soitec (Euronext Paris), recently announced the launch of a joint program to develop and integrate a new layer transfer process within advanced wafer-level multi-chip packaging techniques. Based on the combination of IME’s fan-out wafer-level packaging (FOWLP) and 2.5D through- silicon interposer (TSI) technologies with Soitec’s Smart Cut™ technology, the new cost-competitive process offers higher performance, energy efficiency and increased product yield.

Advanced packaging is used in many of today’s systems-on-chip (SOCs) for servers, high-end mobile, industrial, and automotive applications. Such packaging involves various approaches for combining semiconductor chips into packages to reduce costs, improve power efficiency, and provide efficient heat dissipation. By 2022, the advanced packaging market segment is expected to triple to two million wafer starts for mid- to high-end applications [Source: Yole Development 2017 report for 3D TSV and 2.5D by 12” wafer starts]. The rising complexity of today’s chips with growing numbers of smaller and smaller transistors and circuits requiring high I/O counts is driving collaborative innovation across the advanced packaging process community focused on identifying cost effective solutions for manufacturing, and increased data bandwidth to support hand-held, cloud and edge computing applications.

One of the standard processes in advanced packaging involves using a full silicon wafer for the layer transfer process, which can cost up to 3 cents/mm 2 . Soitec will partner with IME over the next three years to evaluate the use of its Smart Cut™ technology on IME’s advanced packaging platforms FOWLP and 2.5D TSI, with the objective to integrate a new layer transfer process as a key step in future generations of packaging techniques. This new process targets improved performance, lower power consumption and reduced production costs by eliminating the need to consume a full silicon wafer. IME will also conduct tests to evaluate the reliability and robustness of the newly developed process, which will help Soitec to determine its long-term viability.

Smart Cut™ technology makes use of both implantation of light ions and wafer bonding to define and transfer ultra-thin single-crystal layers from one substrate to another. It works like an atomic scalpel and allows active layers to be managed independently from the supporting mechanical substrate. Key benefits include the creation of multiple thin nanometric scale layers of virtually defect-free silicon by utilizing low temperature bond and split techniques. These layers are then placed on top of active transistor circuitry. The thickness of the transferred layer can be determined with a high degree of precision by adjusting the implantation energy and process engineering. Transistors can then be completed using etch and deposition processes. Moreover, the donor substrate can be reused many times as the surface of the silicon wafer is repolished after each layer transfer operation, and the substrate can be reused.

As a leading research institute, IME brings together the global semiconductor supply chain, including fabless companies, foundries, OSATs, EDA suppliers, equipment manufacturers, and materials developers to demonstrate advanced packaging solutions for mobile, data-center, high-performance computing, 5G, IoT and automotive applications. Through this collaboration with Soitec, IME will provide advanced packaging expertise in architecture definition, modeling, design, process-integration, reliability-assessment and failure analysis. IME will execute the advanced packaging development in its fully functional, state-of-the-art 300mm wafer-level packaging, 2.5D/3DIC pilot line. IME’s end-to-end process capabilities and know-how in advanced FOWLP and 2.5D TSI will shorten development cycles and demonstrate cost-effective packaging solutions using Smart Cut™ technology. During the joint program, Soitec will contribute significant tool time, R&D personnel, and dedicated space in its clean room at its Pasir Ris fabrication facility in Singapore.

"Advanced packaging continues to be a bright spot in the high-value semiconductor market. We are excited to partner with Soitec to develop packaging solutions that will contribute to the dynamic growth of this high-potential segment in Singapore and worldwide," said Professor Dim-Lee Kwong, Covering Executive Director, IME.

“Soitec and IME believe Smart Cut™ technology will deliver breakthrough results, revolutionizing 2.5D/3D layer transfer process flow,” said Christophe Maleville, Soitec’s Chief Technology Officer. “This strategic collaboration will not only develop a new Smart Cut™ application serving new generations of advanced packaging, but also open up a brand new market for Soitec beyond traditional engineered substrate manufacturing.”

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