2015 Issues

November • December 2015; Volume 19, Number 6

Chip-to-wafer stacking enabled by 3D integration has significant potential to improve device performance while reducing power consumption. There are many possibilities for collaboration between foundries and OSATs, specifically with ultraprecise stacking (<1μm). Leti‘s roadmap calls for developing fine pitch, from classical thermocompression stacking with copper pillar, to ultra-dense bonding using Cu-Cu technology. Ultra-precise C2W is a promising possibility for the next generation of 3D-ICs.

Photo courtesy of CEA-Leti

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September • October 2015; Volume 19, Number 5

Electronics packaging is constantly evolving to meet the demands for automotive, medical and consumer products that require improved performance. Automotive electronics are among the most demanding in harsh environments and must meet higher standards in order to ensure reliability and safety. Progressive packaging technologies from leaded to surface mount to MEMS, 3D, and die-level packaging will continue to place even more stringent demands on IC packages in these automotive applications.

Photo courtesy of Amkor Technology Inc.

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July • August 2015; Volume 19, Number 4

Package size continues to shrink while the demand for increased performance and reduced power dominate the market. The preferred solution is one that extends advances in IC technology beyond the fab to include 2.5D and 3D assembly. New high-UPH processes using thermocompression bonding (TCB) enables this next-generation of cost-effective high-performance computing and graphics products.

Photo courtesy of Kulicke & Soffa

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May • June 2015; Volume 19, Number 3

The DispenseJet 9500 jets underfill for flip-chips that are attached to an organic substrate strip in an array layout. Using non-contact jetting, the fluid is able to be dispensed close enough to the edge of the device to minimize keep-out zones. Capillary force causes the underfill to flow underneath the die, thereby filling the spaces between the bumps on the die and the substrate.

Photo courtesy of Nordson ASYMTEK

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March • April 2015; Volume 19, Number 2

A DRAM memory stacked on a logic chip using TSVs and micro-bumps. The micro-bump pitch for the connection of memory-logic is 40 μm; the flip-chip bump pitch for the connection of logic-package is 200 μm. The stacking was done using thermo-compression bonding and wafer-level applied underfill. The stack was later assembled on the package substrate using mass reflow and capillary underfill. imec is now assessing similar test vehicles with micro-bump pitch below 5 μm and multiple die stacks for 3D and 2.5D technologies. Photo courtesy of imec

Photo courtesy of imec

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January • February 2015; Volume 19, Number 1

After removal from the FOUP, a 300mm wafer undergoes alignment prior to loading into the Ultratech Superfast 4G Inspection system’s coherent gradient sensing (CGS) interferometry module that will perform full-wafer topology measurement for 3D lithography distortion control. The systematic in-line inspections of the latest technologies, such as second-generation VNAND, 25nm DRAM, and 14nm FinFET, have benefited significantly.

Photo courtesy of Ultratech, Inc.

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