2017 Issues

September • October 2017; Volume 21, Number 5

The photo shows a close-up side-view of the ablation area inside SUSS MicroTec’s ELP300 Excimer Laser stepper. A polyimidecoated silicon wafer is positioned beneath a stationary projection lens (not visible). Bright ablation plumes are visible on the wafer’s surface as polyimide is directly removed by the projected mask pattern and with sub-micron depth accuracy. Excimer laser ablation is a technology enabler and an attractive alternative to photolithography.

Cover photograph courtesy of SUSS MicroTec SE.

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July • August 2017; Volume 21, Number 4

Inside the WaferStorm® Precision Surface Processing System, a 200mm silicon wafer on an automated handler moves toward the proprietary ImmJET™ heated immersion and a high pressure spray chamber. Using a single-wafer wet etch process for wafer thinning, the solvent techniques and advanced process control provide a low-cost alternative to chemical mechanical polishing and plasma dry etch processes for advanced packaging applications.

Cover photograph courtesy o f Veeco Instruments Inc.

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May • June 2017; Volume 21, Number 3

The cover captures the essence of the 50 years of Leti R&D for solutions that encompass a wide variety of sectors, including sustainable transport systems, telecommunications, health, consumer electronics, energy, smart cities, defense and security, and space. Founded in 1967, Leti evolved into a global leader in micro and nanotechnologies tailoring differentiating applicative solutions. Leti has formed partnerships with a multitude of global technology leaders that span a half-century of innovation.

Cover image courtesy of CEA-Leti

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March • April 2017; Volume 21, Number 2

The cover shows a tool operator measuring the total thickness variation of an adhesive interlayer of a temporary bonded wafer by taking 280,000 measurement points. For thickness measurements,a high number of measurement points is needed to achieve proper accuracy. Local deviations,such as particles within the bond interface, have a significant effect on the subsequent thinning process, which can lead to wafer breakage and tool downtime.

Cover image courtesy of EV Group

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January • February 2017; Volume 21, Number 1

The cover shows two different optoelectronic interconnection methods developed to enable photon and electron conversion at the level of the microelectronic (logic) chip. Parallelized optical fibers (front) and lithographically-defined compliant polymer waveguides (behind) carry data in optical form to/from the IC. The flip-chip bumps on each die form the electrical connections to the package substrate. As optoelectronic conversion moves closer to the chip, improved data transfer speeds, bandwidth and power efficiencies are expected.

Cover image courtesy of IBM Corporation

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