An Independent Journal Dedicated to the Advancement of Chip - Scale Electronics January - February 2000 Email the editor

Prohibitive costs and a limited number of ceramic substrates have led to a conversion to organic substrates to perform circuit functions beyond simple interconnection wiring and impedance control.

By Dr. Rao Mahidhara, Contributing Editor

The complex nature of electronics today has resulted in the increasing use of complex devices requiring area-array-type packages. These array packages, which include the BGA and CSP, demand both a high wiring density and a high I/O density.

This density, in turn, reduces mounting real estate and contact pitch, representing new challenges for bare board makers and assemblers.

There are two distinct markets for HDI technology: One market is for product PC boards, driven by reliability, while the other is for IC package substrates, driven by cost.

In addition, roadmaps developed by organizations such as the National Electronic Manufacturing Initiative (NEMI), the IPC and the Semiconductor Industry Association (SIA) to assess the future of HDI substrates, have identified five product sectors.

These sectors take into account key cost and density drivers:

• Low cost (cameras, entertainment)
• Portability (cellular phones, personal digital assistants, sub-notebooks
• Cost/performance (personal computers, system servers, high-end games)
• High performance (super computers, high-end work stations)
• Rugged environment (autos-under hood, military and avionics)

Requirements

Accommodating the BGA package to the high-performance market will require the substrate to have a PTH pitch of 1.00, 0.8, 0.8 and 0.65 mm for the years 1999, 2001, 2003 and 2009, respectively.

There must also be a sufficient number of signal layers to access 12 outer rows below the BGA substrate, as well as metal wiring on the top of the substrate that is accessible to the outer rows with two signal wires routed between two adjacent pads at 0.5 mm pitch.

Thus, there is an immediate need for more complex board designs, incorporating finer via diameters and capture pads, dictated by escape routing calculations that vary with the number of rows of balls and pitch.

Interconnecting Substrates

Opportunities for the innovative structuring of high resolution circuit tracks, as well as drilling a large number of small vias is gaining immense popularity. The desired scale of integration is being enabled by realizing fine- and ultra-fine-line structures, as well as blind via holes that can't be created by conventional structuring methods.

A number of companies are developing HDI boards for portable products. The Japanese first introduced HDI substrates in products such as mobile phones, camcorders, car navigation systems, PC cards and notebook computers. North American and European mobile phone makers then promoted the use of HDI substrates in their products with a close eye on workstation and network systems.

The extreme requirements for chip-pad count and density, derived from the projected silicon technology revolution, have become primary challenges to continued package development and have profoundly influenced substrate technologies.

Fine pitch BGAs/ CSPs at 0.5 mm pitch are also putting pressure on HDI substrates for the I/O escape to reach the inter-level vias or the PTH.

TechSearch International, Austin, Texas, has observed that, on one hand, the via hole and capture pad diameters commonly seen in HDI product substrates are in the range of 150-200 microns and 250-400 microns respectively, with, 65-75 microns line and 75-100 micron spaces, depending on the application.

High I/O counts (in excess of 150) in products that use ASICs and microprocessors, however, have driven the production of HDI substrates for flip-chip, BGA-type IC packages with smaller via holes between 70-80 microns and capture pad diameters of 125-150 microns. Applications are workstations, network systems and many telecommunications products.

PC board manufacturers are becoming increasingly aware of the important issues associated with HDI. These issues include handling thin materials, establishing process controls to etch or plate 50-micron-thin conductors, controlling plating thickness into blind vias or into microvias produced on the surface layer and relamination.

Microvia Technologies

Prohibitive costs and a limited number of ceramic substrates have led to a conversion to organic substrates to perform circuit functions beyond simple interconnection wiring and impedance control. These substrates employ integral inductive/resistive/ capacitive layers for fine-pitch BGAs.

Both the NEMI and SIA roadmaps suggest that all interconnections consist of organic materials, because FR-4 type material is still the least expensive way to make even multilayer PWBs. Some packaging engineers believe that the presence of high I/O flip-chip die will require the use of microvias for the package substrate. In addition to high-density multilayer constructions on a rigid four-to-six layer FR-4 board, as a core, using a non-glass- reinforced dielectric, will be needed.

Microvias, in particular, possess via connections in the attachment land which result in saving board real estate for conductor routing and interconnecting high I/O arrays.

In addition, microvias use smaller lands for both capture of the hole (where the hole starts) and the target land (where the microvia ends). This combination of the two lands is what helps make HDI structures such a useful development for interconnecting area-array packages.

Photo-imageable Materials

Available technologies for microvia HDI formation in the dielectric layers include, laser ablation, photovia techniques, plasma etching, and the less popular vias and circuitry formed by conductive inks.

Economic models and PC board fabricator experience point out that photoimaging (Figure 1) makes sense when the board design requires (40 microvias/sq.centimeter of 75-352 micron via diameter, which means 108,000 vias/35x60 sq. centimeter panel.

NEMI and the Interconnection Technology Research Institute (ITRI) have noted, that, from a fabricator's viewpoint, photovia technology has the lead in infrastructure development. It is the most mature technology with products that demonstrate proven reliability. Photovia formation continues to grow in large volume applications, such as PC boards for portable PCs, where the simultaneous formation of a very large number of microvias offers favorable economics. Figure 1. Via technology roadmap (Source: ESI).

Plasma microvia technologies have fallen to third place, with a few early adopters still supplying product. Unlike the liquid solder mask used early on, modern photo-imageable dielectrics are either liquid or dry unreinforced film, and microvias are formed en mass by photo-imaging.

One advantage of being photo-imageable is that unwanted material is washed off during development, eliminating the planarization step.

While early products did not demonstrate ideal dielectric characteristics, robust via formation capability or good plating adhesion, significant advancements have however resulted in dielectric materials with excellent plating adhesion and excellent photospeed for high resolution.

Non-Reinforced Dielectrics

Unclad non-reinforced dielectrics are photo-imageable and include epoxies, epoxy blends, polynorborenes, polyimides, etc. They can be applied as liquid or dry film, negative or positive imaging. They are solvent or acqueous developable to form 125 to 350 micron blind vias with a low (1:1) aspect ratio.

HDI substrate expert Happy Holden of TechLead Corp. maintains that the unique advantage of photo-imageables is that all vias are produced simultaneously and the speed to make via diameter, line width and spacing smaller than 50-75 micron, is always the same, which enhances productivity-provided yields are good.

In addition, photo-imageables are easy to work with in the creation of three SBU layers with less than 25-50 microns dielectric thickness. Moreover, these materials can also be laser drilled because they are nonreinforced. Cavity formation is also possible, according to Stephan Padlewski of Dupont, although lower process robustness and higher cost are potential weaknesses of the photovia process.

Laser Fabrication

While the photovia process has been a leader early on, thanks to the innovative approach of IBM-Yasu in Japan, TechSearch International observes that laser via fabrication using excimer, CO2 and UV Nd:YAG laser techniques are now becoming the most widely adopted technologies-with several companies offering HDI boards with laser- ablated vias.

Lasers have stepped into the breach due to improvements in laser productivity, the availability of "laser-friendly" materials, via placement accuracy, ease of adoption, lower capital requirements and improved overall yields.

Production costs for using lasers continue to decrease, with a 30 to 50% throughput improvement per year. As a result, both ITRI and NEMI have concluded that laser via formation has overtaken photovia technology both in product volume and number of manufacturing sites.

Japan Leads in Laser Use

As shown in figure 2, in 1998 alone, there were 300 laser units installed in Japan compared to a total of 150 units installed in the US, Europe and Asia, combined. The number of laser units was expected to grow last year to 425 in Japan alone, according to recent estimates. Figure 2. Worldwide laser capability (Courtesy of ESI, NT Information and TechSearch).

Non-reinforced or reinforced copper clad based materials have a longer history forming blind vias than any other material-a fact that is very comforting to many designers, OEMs, and PC board fabricators.

Today, HDI structures are predominantly organic printed boards with laminate substrates, a $30 billion market that will increase to a whopping $50 billion by 2006, according to ESI.

About 85% of these organic boards utilize FR-4 boards to produce copper clad structures, which may be non-reinforced or reinforced. dielectrics with their long history of making. Reinforced dielectrics can be woven glass or non-woven and the reinforcement can be aramid, glass etc. Vias are made by laser drilling using a conformal mask or a directly focused beam, with either a UV:Nd:YAG or a CO² laser.

In addition, unclad, non-reinforced. Copper-coated dielectrics are the most commonly used materials for many build-up multilayer PWBs, and many product variations fit within the existing multilayer manufacturing infrastructure.
Epoxy-based coated foils, available in a variety of thicknesses, are the most common and have performance properties similar to FR-4 but with no E-glass reinforcement. Since build-up technology is still in its infancy, and evolving very fast, many different and diverse approaches are being taken to the resins used and variations on the actual via formation process.

Resins with low dielectric constant (Dk) such as polyphenylene ether (PPE) are being employed to address signal speed and integrity demands in resin-coated foil build-up structures. Via formation is most commonly performed with lasers.

Plateable Resin

Another approach is to employ additively plateable resin and use the copper as a sacrificial carrier, eliminating the need to laser through copper, resulting in excellent surface topography and peel strengths.

Example products are Allied-Signal RCC, Polyclad PCL, Mitsui and Hitachi (MCL-6000), MCF-9000 GEA 679P.

Among the non-woven, non-glass reinforced laminates with lower Dk and CTE that may be photo-imageable are IBM's High Performance Chip Carrier, W.L.Gore's SpeedBoard-a PTFE-like laminate, and DuPont's aramid materials, such as Thermount and Thermount RT.

Dry or Wet Etching

The plasma process involves dry etching using microwave-gas plasma on the copper layer and the underlying dielectric and provides the advantage that all of the vias are produced at the same time, permitting several panels to be processed simultaneously.

The plasma drill is easiest to install and lowest in capital costs, according to TechLead's Holden. However, the long cycle time cancels the benefits of mass microvia creation making the overall approach relatively slow and not widely accepted.

Wet etching by hot KOH has been used for polyimide films. Both dry and wet etching processes are isotropic because etching is performed inwards into the film with the danger of undercut beneath the copper layer. On the positive side, all these vias are formed simultaneously without regard to diameter or number.

Chip Shrink

Today's BGAs/CSPs are employed in low pin count applications with the potential advantages of higher performance and chip shrink transparency to optimize productivity.

Chip shrink will warrant a scale-up of flip-chip pitch with respect to silicon features. This will result in a corresponding redesign of the substrate onto which the packages are assembled for the final product. There will also be a decrease in cost/layer, while scaling the wiring density with a flip-chip pitch reduction.

Conclusion

The importance of HDI will not wane in the foreseeable future. While the potential for this technology is great, its contact and interconnect density, coupled with the manufacturing cost goals in the later generations, is not necessarily achievable with existing technology.

The 70 microns pad size, projected in 1999 on various industry roadmaps, is a major limitation and cost-prohibitive with today's organic substrates.

Successful implementation will require either the depopulation of a significant number of pads or a paradigm shift towards multilayer or high density interconnection (microvia) designs on one or both sides of the PC board to support wiring for closely spaced devices and/or provide the escape routing from internal connections of array component patterns.

Readers may contact Dr. Mahidhara at rmahidhara@kns.com.