For some time now, many ASIC manufacturers have been marketing their wares as "systems-on-a-chip," and compared to preceding generations of products, the name probably fits. The change from single-purpose VLSI components (bus controllers, interface controllers, interrupt controllers, graphics, communications, etc.) to devices that combine almost everything on one monolithic IC has wildly impacted several steps in the manufacturing process. Consider that designers need incrementally better CAD tooling to weld these large "super-cells" together in a coherent and efficient manner. Moreover, the fab processes needed to take a quantum leap so that these SOCs would have meaningful yields at acceptable cost. Packaging technology has also advanced to create
a package able to take advantage of performance gains and higher
board density opportunities. There were many other points that needed
improvement, but the ones I've mentioned have been acknowledged
by industry executives as needing care and feeding. Test was ignored until the first components arrived. It then became obvious that SOCs had created a huge test challenge. The ATE industry has been playing catch-up ever since. And while this battle is far from won, especially for high-performance applications, test has taken on a new urgency. Now, however, another challenge looms on the horizon, and this one involves a new breed of module: the "system-in-a-package" (SIAP). This format will tax ATE software and hardware as never before. Take, for example, a stacked CSP for cell phones that includes a Flash and an SRAM memory die in the same module-two relatively simple die in a space-saving package. Why is this a problem? To test the proprietary functions in most components, the manufacturer will often use a high voltage (e.g. 12v) on certain pins as a nonuser enable or chip select. On many current devices, the stacked version of the device requires twice as much current at this high voltage monolithic version of each die type. The IC maker feels that the ßash memory tester or the SRAM tester should be able to handle the stacked version of the device. Because of the doubling of current, however, this is no longer true. Instead, a new high power supply must be created, or a custom solution must be devised, to test the "new" device. Much capital equipment will be affected. At the very least, everything will become more expensive and will take longer. Pre-emptive Measures A few pre-emptive measures should be considered when developing SIAPs and the accompanying test strategy. The first is to ensure that the SIAP's individual CSP components are tested as fully as possible before they reach the integration step in the manufacturing ßow. If possible, all testing that is not directly related to the final function of the SIAP should be executed when each device is still singular. Thus, the Flash memory should have already received its reliability cycling, the DRAM its burn-in, etc. Another critical step, and one that involves some commercial compromise, is to ensure that extra test access points are left available to the ATE, enabling access to any proprietary modes of the devices in the system. If isolation of the various system components will enable easier test development-or the use of less expensive test equipment-then this, too, should be considered. A small isolation ASIC or PLD on the substrate may prove to be of enormous test consequence, and the inclusion of a serial scan interface may be of great help too. There are many potential traps in testing SIAPs, but most of them can be avoided if test requirements are considered at the outset.
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