An Independent Journal Dedicated to the Advancement of Chip - Scale Electronics January - February 2000 Email the editor

Sunnyvale, Calif.-Tru-Si Technologies says it has discovered "a unique, yet remarkably simple method" of stacking multiple chips by stacking wafers containing different circuit functions, such as memory, logic, analog and digital. The result, the company says, is a new concept in three-dimensional, stacked wafer-level packaging, as well as a new, three-dimensional Moore's Law. (Named after Intel's Dr. Gordon Moore, the law claims that about every two years, the number of transistors per chip area doubles.) The Tru-Si process, which offers the economies of scale inherent in processing whole wafers, provides thru-silicon vertical interconnects between the front and back sides of a wafer. Tru-Si says the end result is somewhat analogous to the thru-holes in PC boards.

Dr. Savastiouk

The goal of the technology, according to Dr. Sergey Savastiouk, Tru-Si CEO, is to create a stack of 10 wafers equal to the height of a single wafer.

To date, the primary technical challenge to mass producing high-density, vertically integrated modules has been forming die interconnects within a vertical chip stack. Flip-chip does not allow for interconnecting more than two chips, and wire bonding is limited to the number of chips that can be efficiently stacked, requiring manufacturers to link chips over edges.

The technology employed is based on the company's atmospheric downstream plasma (ADP) etching process, which was introduced at SEMICON West in 1998. Dr. Savastiouk says the ADP equipment "has already been characterized by 30 or 40 different companies."

Damage-Free Wafer Thinning

Initially, the market thrust of the ADP process, according to Dr. Savastiouk, was for damage-free wafer thinning down to 50 microns in one high-yield step. "Now we have found that this same technology can be used to enable vertical miniaturization (and interconnection)."

The result of the process, he adds, allows for the introduction of a new three-dimensional Moore's Law doubling of IC density about every two years in three-dimensional stacked silicon-rather than on the surface of the silicon area-as Moore's Law maintains.

Asked if the Tru-Si process of vertical stacking has been implemented, Dr. Savastiouk reported, "We are in the process of joint development projects with several companies, including major IC makers whom we can't name."

The SEM photo shows a bump of about 30 microns in heighth, with exposed Al in the center. On the edge between metal and Si is a short piece of SiO₂ , serving as the isolation between the Si and the metal. "That was the big deal," says Dr. Savastiouk, "because many people tried but failed to create those contact pads, which were isolated on the backside."

The Process

The first step in making thru-silicon wafer-to-wafer interconnects involves forming deep isolated metal vias (50-150 microns deep) on the front side of a wafer that is connected to the circuitry's appropriate layers. Next, the wafer is thinned using the ADP process, which selectively removes silicon from the wafer's backside, carefully exposing the deep thru-silicon vias without any mask. SEM photo (on the right) showing a bump height of about 30 microns after treating a wafer with Tru-Si's ADP process. (Tru-Si Technologies)

The natural etch selectivity of ADP enhances the simplicity of the process, ensuring a clean, highly reliable formation of rigid thru-silicon contacts on the wafer's backside, according to Dr. Savastiouk. These backside contacts offer flip-chip type performance characteristics and can be bonded to another wafer or substrate without an extra bumping process.-Ron Iscoff [trusi.com]