While strip testing, as well as testing at the wafer level will influence future package handling developments, mainstream acceptance of these technologies is still several years away.By Ralph Henderer, Entegris Inc., Chaska, Minn. The next decade holds a variety of new ideas and new processes for producing chip-scale packages, many of which will impact the installed base of test and assembly equipment-tray-based equipment-to be precise. Strip testing is still 3-5 years away from being accepted as a mainstream approach. In the interim, where do we go and what do we do for CSP inter- and intra-machine transport? There are many proposed solutions, but not all are necessarily feasible. This article will focus on existing solutions. Until CSP strip test and wafer-level testing practices are well accepted, let's make sure that we understand how these and other emerging technologies may affect tray-based handling. Transport Media Today's IC assembly practices, for the most part, use JEDEC-style trays (figures 1-2) as transport media between operations-particularly test handlers. JEDEC trays have traditionally been designed to hold as many components as possible to reduce the cost per unit and to maximize equipment utilization.
To avoid these issues, IC manufacturers have opted to stay with tradition by not shrinking the package with the die shrink, by standardizing on the outside form factor-allowing the shrinks to occur in the package. Once the economics are acceptable, the possibilities of reducing the overall package become feasible. Other manufacturers, meanwhile, continue to blaze forward where few have ventured-into strip test-where a number of issues have yet to be resolved. Also relevent is the move to wafer-level packaging (WLP), which operates on the principle of forming first-level interconnections on the chip before the wafer is sawn. WLP produces a packaged and tested product prior to singulation. Consider that IC test handler providers acknowledge that they will handle "something round" in the future, but are not really sure when "the future" will occur.
The question, then, is will it be CSP strip testing or WLP-or will the two converge? It's too early to say. However, even among the many uncertainties, there are several short-term solutions that exist to help bridge the gap. The Issues The first issue is high volume production vs. brief product life cycles. Because the packaged IC size has historically remained the same, volume production has been based on the availability of material, the number of cavities and open tools. But for CSPs, whose overall size is affected by die shrink, product life cycles become shorter, and the need to retool creates costs which are passed along to the customer. (A majority of the JEDEC trays developed for a specific CSP use or outline require dedicated tooling (figure 3).
Existing Inventory The second issue, which further complicates the frequent requirement to retool, is the "downstream" need to purge old packaging media inventory from the manufacturing floor to prevent them from getting into current inventory. What happens once the die shrinks and the packaging media are no longer useful? Manufacturers must be able to quickly differentiate and dispose of inventories in an efficient manner. Often the changes to trays are so subtle, that they are virtually undetectable to the human eye, which poses, potentially, a very serious problem since obsolete media can damage and even ruin entire chip runs. Color-coding of packaging media with colored resins, labels, painted pin stripes or even snap-on tags is one interim option to help identify inventories for purging or segregation within the work environment. However, this solution raises the issue of secondary costs. Driven, for the most part, by the automotive industry, the ability to trace a component back to its material level is becoming mandatory. With many large-scale items, such as cars, now depending heavily on IC technology from a variety of manufacturers, the need to differentiate becomes necessary from a recall standpoint. IC makers are starting to employ bar codes on trays and other process carriers, media, laser scribing on trays and are even looking at utilizing radio frequency (RF) identification systems for all back end processes. This too, however, can cost more. Miniaturization The fourth issue involves the continued miniaturization of dimensions in process technology, which is a driving force in industry research. As components become smaller and packaging constraints increase, ever-shrinking die sizes contribute to geometry problems. As the industry begins to see components with I/Os populated to the edge, like many FBGA packages today, handling problems arise. As solder balls creep closer to the edge, sufficient handling room becomes a concern. Not so obvious, however, is when manufacturers develop derivative packages in the same form factor, but increase functionality-populating the IO to the perimeter. If the edge-peripheral pattern was not anticipated during original package development, all associated packaging media, as well as test sockets, may be rendered useless and retooling is required. Standard Will Be Matrix The final issue involves the need for a standard matrix. While many CSP and NCSP packages have been registered with the major standards organizations, such as JEDEC and EIAJ, registration for the accompanying tray is not included. In the open market, we see various tray matrices for a given CSP, but again, no JEDEC standard, resulting in an in unnecessary proliferation of JEDEC trays. Tray matrices are calculated in accordance with JEDEC tray design guidelines (Pub-95, Section 10), but if the CSP's size decreases sufficiently, a different matrix may be needed. A change in matrix for a given package results in retrofitting existing equipment with changeover kits. Specifications Simply because a manufacturer designs a tray to JEDEC specifications does not make that tray an industry standard. Tray suppliers must still register their trays. An alternate technique to employing a standard matrix is to place wafflepack trays inside a JEDEC-compliant tray, thus providing an interface to existing equipment sets. This tray-in-tray concept is quite feasible-particularly for low volume applications where product life is minimal. Ironically, even within the standard packaged IC environment today, the marketplace has moved to unique trays or carrier tape to handle each OEM's package. While we need to push for the standard matrix approach. We can offer a unique form factor for a unique package on a local level, but we should have a common denominator at some level, and that common denominator is a standard tray or matrix array. A standard matrix provides several advantages. First it presents tray suppliers with an easier platform to provide the next size package tray in a timely and cost-efficient manner without redevelopment. It also allows the semiconductor maker to avoid the cost of changeover kits and reprogramming equipment. Materials The final issue, which is closely tied to the move to wafer-level packaging, is the need for cleaner materials. This will definitely be a major issue and a paradigm shift as the industry sees more and more of the back-end packaging processes move into class 10,000 and class 1,000 cleanroom environments. The cleanliness issue will also put a bind on suppliers of trays and of the materials used. Another important consideration is getting the industry to define "what's clean and what's not?" At a minimum, delivering product packaged in cleanroom media will be required-even having to clean the material before it is used is a strong possibility. Certainly, the migration to such advanced technologies as WLP will compound the situation. In the semiconductor industry, the end markets typically dictate what's needed-and the market today is placing emphasis on consumer products. The industry research firm Dataquest indicates that, "The three main drivers for the semiconductor market are PCs, consumer electronics and communications." Conclusion Whether or not the tray-based market will still see growth, in light of CSP strip test and WLP, is unknown-at least for now. The thing to remember is "don't reinvent the wheel." (figure 4 depicts a timeline showing the gaps in technology that must be bridged.)
References 1. V. Solberg, "Adapting Waffle Packs to the JEDEC Tray Format," Chip Scale Review, January-February 1999. 2. "Dataquest Places Chip Market at $244B by 2003," Chip Scale Review, July-August 1999.
|
