Wafer-level packaging (WLP) is a true technological revolution that promises to have a profound impact on electronics for decades to come. Like the through-hole and SMT revolutions before it, WLP is driven by increases in the density of connections to the chip. As in any revolution, the far ranging consequences are often difficult to foresee on the basis of the initial trickle of events. The term "wafer-level packaging" has been applied throughout the industry in many ways and often ambiguously. It most accurately describes, however, the processes for making chip-scale packages directly on the wafer, rather than the type of package construction that is employed. The advent of WLP is an inevitable result of
the move toward CSPs. By shrinking the package to the size of the
chip, each package fits within its site on the wafer, where it is
fabricated and then diced into complete ICs. Although still in their infancy, wafer-level technologies of every conceivable type are beginning to emerge from R&D laboratories around the world. Initially, WLP is being driven by the cost reduction that results from fabricating packages in a batch mode, rather than assembling individual discrete components. Instead of attaching bond wires individually, a full wafer of packages is fabricated in a batch mode on the wafer, similar to the way transistors are fabricated in ICs.
WLP enables learning curve efficiencies in IC packaging, and offers a significant improvement over a price plateau that has been stagnant at a penny a pin for decades. Beyond improvements in manufacturing efficiency, however, WLP offers a cost reduction due to wafer-level burn-in and test accomplished prior to wafer dicing. This allows the traditional wafer probe and die marking steps to be eliminated completely at a significant savings. Once established in the industry, WLP will be used to achieve performance advances not attainable with interconnections on the chip itself. Power and ground distribution are done more easily by using copper planes in the packaging layers to obtain the clean power needed for low voltage, high-performance chips. Global Wiring High performance global wiring can be implemented more effectively in shielded copper traces in the package than in double damascene copper on the wafer. At that stage, chip and package will begin to merge into one fully integrated system, without the delineation between high tech wafer fab and off-shore packaging backend that exists today. Techniques employed in WLP will impact the design and assembly of electronic systems, with significant improvements in connectors, wiring substrates, sockets, thermal management and design as system components rush to keep up with advances in CSP density and performance. We need to consider the broader view, and not just the package, to see the causal links that will shape interconnect technology for some time to come.WLP is clearly a technology that bears watching. This column will track developments in this rapidly emerging field and attempt to project WLP's impact on electronics, as we peer into the 21st century.
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