Our Experts: Dr. Thomas H. Di Stefano is a pioneer in the chip-scale packaging area and the co-founder of Tessera, San Jose. Prior to Tessera, he was a senior manager at IBM, where he spent nearly two decades. He is the holder of numerous patents in IC packaging and the author of dozens of articles on chip-scale packaging. He earned a Ph.D. in physics from Stanford University. He currently is the president of Decision Track, San Jose, a technology incubator and consultancy. [tomd@decisiontrack.com] Dr. Kevin E. Howard is an EMI Shielding Development Leader in Dow Chemical Company's Materials Sciences and Information Research Division, Midland, Mich. His earned his Ph.D. in inorganic chemistry from the University of Illinois, Urbana-Champaign. Dr. Howard was named a Dow Inventor of the Year in 1995. [kehoward@dow.com] Dr. Guna S. Selvaduray is a professor and graduate coordinator in the Department of Chemicals and Materials Engineering at San Jose State University. He earned a Ph.D. in metallurgy from Stanford University, a master's in materials science and engineering, also from Stanford, and a B.Eng in mechanical engineering from the Tokyo Institute of Technology. A Registered Professional Engineer, he is fluent in five languages. [gunas@email.sjsu.edu] Hem Takiar is the Director of the Package Technology Group at National Semiconductor Corp., Santa Clara, Calif., and a prolific author in the field of packaging. Leave room for one more sentence. [hem.takiar@nsc.com] Dr. Dan Tracy is a Senior Market Analyst in SEMI's Industry Research and Statistics Group, Jose. Before joining SEMI, recently, he was a consultant with Rose & Associates, Los Altos, Calif. He earlier worked for National Semiconductor, Santa Clara, Calif. Dr. Tracy earned a Ph.D. in materials engineering from the Rensselaer Polytechnic Institute, Troy, N.Y. [dtracy@semi.org] Dr. C.P. Wong is a Regents professor at the School of Materials Science and Engineering, and a Research Director at the NSF Packaging Research Center at the Georgia Institute of Technology. He received a bachelor's degree in chemistry from Purdue University and a Ph.D., also in chemistry, from Pennsylvania State University. Dr. Wong also spent 19 years at AT&T Bell Labs and was elected a Bell Labs Fellow in 1992. He currently chaired the IEEE/ IMAPS International Symposium on Advanced Packaging Materials in 1999 and 2000. He was recently elected a member of the National Academy of Engineering. [cp.wong@mse.gatech.edu] Dr. Thomas H. DiStefano Surveying the past several years in electronics hardware, we find two areas that stand out as showing exceptionally high growth: chip-scale packaging and microvia substrates. Demand for both has doubled year-after-year, driven by an explosive growth in wireless applications. What's behind this growth? It's people like you and me who demand ever smaller cell phones and other personal electronics. We are willing to pay a premium for a sleek product, often more than the cost of the base function itself! Put differently, how much would you pay for a cell phone the size of yesterday's conventional handset. Probably nothing, right? Looking ahead, expect this trend to broaden, fueling continued growth in CSPs and microvia substrates of various kinds. These two areas go hand-in-hand, as CSPs often require high-density substrates to wire the fine-pitch grids. The growth rate of CSPs into new applications, particularly those for high I/O devices, is paced by the availability of cost-effective microvia substrates. This linkage is particularly true for wafer level CSPs where the contact bumps must fit in a high-density array in the shadow of the die. We must consider these factors together in anticipating events. First, expect growth of CSPs to continue for low pincount ICs (Flash, SRAM, DRAM, DSPs and other I/O devices) that can be assembled on low cost substrates. Wafer level processing of CSPs, often little more than dressed-up flip-chips, is moving into the mainstream beginning with small, low I/O chips for which substrate density and thermal expansion mismatch is less important. Becoming firmly entrenched in low I/O applications, CSPs will move up to more complex applications as the infrastructure for high-density interconnect develops. Japan is well ahead in microvia substrates and wafer-level packaging-which are considered strategic enablers for miniaturization and performance. We will see these advances embodied in sleek and sophisticated personal electronics. As in the early days of SMT, high-density packaging technology will propagate out from its early applications to pervade all of electronics, creating whole new businesses in its wake. Dr. Kevin E. Howard The implementation of copper interconnects and low-k dielectric materials will lead to reduced feature sizes and increased functionality and operating speed. With IC's now operating in the GHz range, thermal demands will once again be an area of concern in advanced packaging. High-performance packaging, utilizing various thermal enhancement techniques and materials, will be an area of focus. Concomitantly, thermal performance testing will continue in importance. Additionally, electromagnetic compatibility of high frequency components and the management of EMC in portable devices may be a focus issue, with some impact on packaging and integration into devices. While both thermal performance and electromagnetic interference are independent issues, materials science opportunities may be considered that can achieve a resolution to both problems simultaneously. Dr. Guna S. Selvaduray "Smaller, faster, cheaper" have become the standard buzzwords of the semiconductor assembly industry. But to achieve these size, speed and cost goals, new enabling technologies are necessary. Even while OEMs and end users are demanding "smaller, faster,cheaper, the packaging engineer is being deluded with an increasing number of chip designs-with each manufacturer claiming the virtues of his own designs, yet telling us very little about the limitations, not just in performance and reliability, but also in terms of manufacturability. So, first, we need to change our buzzwords to "manufacturable, designable, testable and reliable." Somewhere, in there, we need to include the words "environmentally friendly." If we develop the smaller, faster products with these words in mind, we will automatically achieve the "cheaper." Despite being an integral part of the computer revolution, I have yet to see an expert system that a design engineer can use to identify and select the most appropriate design for his/her product. Perhaps the time has come for the industry to come together and work on establishing an expert system that will enable end users to pick the best product for their designs. This may put some of the marketing people out of work. However,if the customer can select a particular component, design, vendor or material without ever having to see a marketing person, wouldn't that be the most cost-effective way to market? Hem Takiar Look for a significant increase in the use of wafer-level CSPs, with 10-20X as many new end products employing devices packaged at the wafer-level. Expect, however, that the number of technology approaches for wafer-level CSP will be consolidated to three-five approaches. (Primarily based on the use of eutectic solder balls). I also anticipate a slow migration toward the use of lead-free solders-as well as a wide acceptance of molded CSPs (wire bonded) for most surface-mount based assemblies. Other likely scenarios in assembly and test:
Dr. Daniel P. Tracy I expect to see movement within the BGA and CSP substrate supplier base, a market segment that has already seen many changes in the past several years. A number of new suppliers have entered the laminate and tape substrate markets in the past few years, including 10 leadframe suppliers. In the high-end substrate market, several major suppliers have dropped out of the market altogether, or have re-vamped their strategic business plans. More changes will occur as suppliers drop out, form joint ventures or eventually gobble-up one another. Consolidation will likely be the name of the game in the substrate market for 2001 and beyond. Lead-free solder initiatives will continue to be marked with uncertainties, as the industry attempts to sort through available lead finishes, board/substrate finishes and alternative solder ball technologies. There remains a sense of "what to do now" and "what to do next," and it appears that there will be, for some time, more than one lead-free solder solution. Package subcontractors are in difficult straits, because they may have to maintain multiple plating lines-one for eutectic tin-lead and others for tin, tin-copper, or even tin-bismuth. Bumping houses are experiencing the same uncertainty, as some customers are inquiring about lead-free alternatives, while other customers have requested high lead solder bumping! It will be extremely interesting to observe how the timing and implementation of lead-free solders will sort out during the next several years. One thing is certain; lead-free initiatives will keep packaging engineers quite busy. Prof. C.P. Wong Since the development of flip-chip technology for high performance IC interconnects over 40 years ago, this technology has chiefly been used in high-performance microprocessors and ASIC on expensive ceramic and silicon susbstrates. However, ever since low-cost flip-chip on organic substrate was demonstrated by IBM Yasu Labs in Japan, flip-chip technology has been gaining acceptance in the industry. With recent developments in under-bump metallization, the many sources of FC bumping facilities available in the US, far east and European community, and the advances of the infrastructure in flip-chip equipment, such as pick-and-place, flip-chip bonders, dispensing equipment, etc., the technology is gaining speed in low cost ,high-performance packaging. The advances in underfill technology include: 1. Conventional capillarly flow underfills 2. No-flow (compressive) underfills 3. Molded underfills and 4. Wafer-level underfill. These materials and processes are making advances in the technology widely available to many packages. Recently, the reworkable underfills-either the conventional capillary flow or no-flow materials-have become available to the market, advancing further the role of flip-chip. In the next decade, we will see more flip-chip on low cost packages in all handheld, cost-constrained and high performance portable, wireless consumer products. |
