This month issue An Independent Journal Dedicated to the Advancement of Chip - Scale Electronics January - February 2001 Email the editor

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II. EXCHANGING DIE DATA

In Part I, we described how packaging foundries can organize information about their existing packages in a way that easily enables users to select one based on type, size and power dissipation.

For the majority of new chip designs, a custom package must be designed, generally using laminate technology and a ball grid array. There are two reasons why a custom package is needed:

1. Constrained Routing, where the pinout must match a pre-conceived pattern. Moving the signals locations to accommodate an existing package is not an option.

2. Wirebonding Limitations, where even shrinking a die by 20 percent may prevent it from being placed in the existing package, because the wires from die pad to bond finger may be too long.

For high IO die, it is critical to work with the package designer early on. Package designers need to deal with two major issues on a new design:

• Can I wirebond all the die pads?

• Can I route all signals to their destination?

Either the chip designer or the package designer should do both bonding and routing feasibility studies before the chip layout is fixed. We've found that too much effort is expended in converting the IC designer's data into the formats required for the package design tools.

The AIF Format

In an effort to speed up both feasibility studies and package design, several packaging OEMs worked together to create a standard format known as AIF2 (Advanced Input Format). This is a simple ASCII file that can be imported easily into the major package design software. It consists of die pad numbers, x,y coordinates, a signal net and a destination pin or JEDEC ball number (Figure 6). IC designers can easily assemble such a table except perhaps for the destination pin. However there is always the possibility of introducing error.

Figure 6. The AIF file format

III. WEB-BASED TOOLS

To encourage the adoption of the AIF format, we developed a simple and free tool that reads the AIF file by either reporting errors in syntax, or if the syntax is correct, creating a drawing of the die with pad numbering and labels, as shown in Figure 7. One can access the AIF reader anytime, from anywhere, using only a WEB brower.

Figure 7. To verify the AIF file, we wrote a program that reads the file, checks it for syntax and returns either a syntax error, or if no errors are found, a drawing of the die.

Since all computation is done on the server, the AIF reader is platform- and browser independent.

User Interface

The AIF reader's user interface is intuitive to anyone who has used a WEB browser. Once the designer has composed an AIF file, the designer uses the "Browse" button to select the file for upload (Figure 8). The user also decides whether the drawing should be returned as .dwg, .dxf or .pdf files, and more file options are in preparation.

Figure 8. The Web interface for the AIF reader

Should the AIF file contain syntax errors or other errors (for example, the same die pad assigned to different nets) then the returned page will list the errors and their causes (Figure 9). In this case, the line refers to SQ800 but the user defined the padstack as SQ80. After editing the file and resubmitting it, the file runs successfully and a link to the graphic file is returned.

Figure 9. Syntax error return; The designer typed SQ800, but should have typed SQ80.

A simple but effective way to predict the routability of a BGA style package is to first examine a simple rats nest from die pad to destination balls. Though this does not take into account wirebonds, it does immediately identify if any of the die pads are destined for locations that will block the routing of other nets.

Figure 10. If no errors are found in the AIF file, it is converted into a DWG file and the user receives a link to the file.

By examining the rats nest, one visually identifies "high density" areas that may be difficult to route, and it's easy to spot signals that cut across many other routes. Such paths often act as barriers that block routing or force additional vias on multilayer designs. Often, a minor change in a die pad signal assignment simplifies the routing of the package.

Figure 11. The array generator module defines the location of the ball pads. A vector can be drawn from each die pad to the assigned ball pad based on the netlist.

The AIF reader can be extended into a WEB based rats nest generator. All that is needed is a second module that places the JEDEC balls in their proper location. A vector from each die pad to the assigned ball generates the ratsnest. Die pads and balls assigned to power and ground nets are normally ignored, although they can be color coded to give a visual indication of where power and ground nets or bars will be placed.

Figure 12. the returned drawing now includes a ball pads and a rats nest in addition to the die pads.

Summary

It is unnecessary to implement large, expensive and sophisticated software to improve collaboration between the IC designer and the chip designer. A simple Web server coupled with a program to select parts makes it easy for IC designers to find out if an existing package will meet their requirements.

A simple program tied to a Web server enables IC designers to test a standard file format for exchanging data with package designers. An extension to that simple program enables a designer to create a rats nest useful for routing feasibility studies. In the near future, two additional modules will be offered, including a dummy die generator and a signal assignment advisor. Too see a demonstration of the modules described, visit wirebondonline.com.