This month issue An Independent Journal Dedicated to the Advancement of Chip - Scale Electronics January - February 2001 Email the editor

By Abid Merchant, DuPont Fluoroproducts, Wilmington, Del., and Mike Bixenman, Kyzen Corp., Nashville, Tenn.

Organic flux residues deposited onto the surfaces of flip-chip assemblies during reflow soldering operations have been shown to affect reliability adversely, while cleaning prior to underfilling will dramatically improve reliability.

Corrosion-related failures in flip-chip interconnect systems occur in two forms: in the solder interconnect or on the chip or substrate metallization. The chemical reactivity of the solder joint, as well as the environment, influence the kinetics of corrosion.

High temperature and humidity conditions and reactive halides (e.g., from the underfill or flux residues) can accelerate corrosion-related failure. This article will discuss how the removal of flux residues using HFC vapor phase technology allows underfill materials to adhere and flow under the die without restriction.

Flip-Chip Process Dilemma

Flip-chip is a rapidly growing segment, and demand for flip-chip assemblies is projected to grow 500-1000% over the next five years(1). The technology offers a number of advantages over standard wire bonding, such as self-entering during assembly, size reduction, dense full-area array footprints to accommodate higher I/O and enhanced electrical/thermal performance.

Underfill is used to improve the reliability of flip-chip interconnect systems. These materials fill the gap between the chip and the substrate around the solder joints, reducing the thermal stresses imposed on the solder joint.

High adhesion of the underfill material to the substrate and die is necessary to improve the reliability of the interconnect system. Flux residues deposited onto the surface of flip-chip assemblies during reflow soldering operations have been shown, in some cases, to affect the adhesive and flow properties of underfill materials. Moreover, results of thermal cycle tests and humidity storage show that the reliability of flip-chip packages is dramatically reduced by flux/underfill incompatibility(2).

Cleaning Challenge

Flip-chip poses a very difficult cleaning challenge. While the package size continues to decrease, the total number of I/O continues to increase.

As the I/O increases, the array density of the package increases, and as the array density increases, the pitch decreases. If the pitch is decreasing, the standoff is also decreasing, which means that the package is getting smaller, the number of obstacles is increasing and the distance between the substrate and the die is decreasing.

Consequently, with the overall miniaturization of the package, coupled with the fact that there may be more than one die per package, as well as added variations due to choices in raw materials, it is not difficult to understand why there would be challenges with cleaning flip-chip assemblies.

Figure 1 illustrates why cleaning under a flip-chip is a difficult challenge(3).

Figure 1. This cutaway illustrates why cleaning under a flip-chip is a difficult challenge.

Product Reliability

Flux removal techniques have been used in many electronics manufacturing and assembly processes as a means of assuring consistent material properties and improving product reliability. These cleaning techniques typically provide clean bonding surfaces for enhanced device reliability.

Cleaning techniques used for flip-chip assembly processes require a cleaning chemistry with desirable properties, such as low surface tension and viscosity to assure penetration under the die, flux contaminant solubility and residue free rinsing.

Should the chemistry or rinse media be left under the die, there would be a degradation of underfill flow properties, including inconsistent flow patterns, the generation of voids during underfill cure and poor interfacial bond strengths. Therefore, selection of the cleaning chemistry and process is critical for successful cleaning under the flip-chip die.

Vapor Phase Technology

Solvent defluxing is a popular method for cleaning electronic assemblies. Vapor phase solvent blends possess good wetting characteristics to assure flow and wetting in all areas under flip-chip die, which allows dissolution and removal of flux residues.

Extremely low viscosity and surface tension enhance the wetting and flow characteristics required to clean flip-chip assemblies. CFCs fit this category of solvents but have been eliminated as alternatives due to their ozone depleting potential. In addition, hydrochlorocarbons and bromocompounds pose questions concerning toxicity or carcinogenicity and may be too aggressive to some plastics and elastomeric materials.

The selection of suitable solvent defluxing chemistries requires non-ozone depletion, low toxicity and cleaning efficacy.

HFC Technology: Hydrofluorocar-bons are a family of compounds containing carbon, fluorine and hydrogen. The absence of chlorine in the hydrofluorocarbon molecules makes them non-ozone-depleting substances.

The presence of the hydrogen atom(s) reduces atmospheric life; therefore, these compounds have significantly lower GWP (global warming potential) than similar fully fluorinated or chlorofluorocarbon compounds. The presence of a large number of fluorine atoms tends to make these compounds non-flammable, low in toxicity, stable to heat, low in reactivity, and compatible with most materials of construction.

Physical Properties

A hydrofluorocarbon containing 5 carbon, 2 hydrogen and 10 fluorine atoms (CF3CFHCFHCF2CF3) named HFC-43-10mee has physical properties similar to or better than CFC-113. Compared to CFC-113, this HFC has a very low surface tension, a higher boiling point, and a lower heat of vaporization so that it dries rapidly without leaving any residue.

These properties, combined with non-flammability, chemical and thermal stability, low toxicity and ease of recovery by distillation, make this HFC ideal for cleaning IC packages. Solvency lies between CFC-113 and PFC (perfluorocarbons) and can be enhanced significantly by use of appropriate azeotropes and blends with alcohol, hydrocarbons, esters and hydrochlororcarbons.

Ideal for Demanding Requirements

Flip-chip technology has focused engineering development toward a no-clean process. This approach works well on peripheral and low I/O substrates.

As the area density goes up, flux residues trapped around the base of the solder bump have the potential to affect adhesion and create voids under the die. To enhance reliability, cleaning may be a requirement. The cleaning solvent must have extremely low surface tension and viscosity, defluxing solvency and be dry residue free. This highly difficult cleaning task favors a vapor phase process.

HFC-43-10mee possesses all the desirable properties, with the exception of one critical parameter: cleaning efficacy for the flux residues. Since the chemistry of soils varies greatly, the chemistry of a cleaning agent must be similarly adjusted to remove the selected soil.

HFC-43-10mee can be effectively blended with a variety of other solvents to form specialized cleaning agents for difficult cleaning requirements such as flip-chip. The resulting formulations inherit the desirable properties of the parent chemicals such as low toxicity, non-flammability, good compatibility, good thermal and chemical stability and selective solvency.

Figure 2. These acoustic micrographs show die that were not cleaned compared to die cleaned with HFC technology.

Available Materials

A careful and thorough search was made of the available materials for preparing the HFC-43-10mee-based flip-chip formulation.

The materials qualified for blending must offer properties that enhance the performance of neat HFC-43-10mee for removal of flux residues.

The candidates were further screened to pick those that would either form azeotropes or behave like azeotropes. Selecting those formulations that would be non-flammable, based on Dept. of Transportation flash point tests, further screened the candidates. Based on these criteria the candidates that met these requirements were alcohols (methanol, ethanol and isopropanol), hydrocarbons (cyclopentane and heptane) and 1,2-transdichloroethylene.

1,2-transdichloroethylene (Trans DCE) contains chlorine, but the presence of hydrogen and the double bond makes the molecule reactive in the lower stratosphere. Therefore, it has nearly zero ozone depletion potential.

Trans DCE has excellent solvency for higher molecular hydrocarbon oils and greases as well as flux. Also, the permissible exposure limit of Trans DCE is 200 ppm, the same as that of HFC-43-10mee. Trans DCE is flammable, but the presence of HFC-43-10mee in the composition suppresses flammability. Formulations have been compounded and the data suggests superior cleaning under flip-chip die.

Experimental Procedure

Flip-chip test assemblies were produced to demonstrate the effectiveness of an HFC formulation in removing a low solids no-clean flux prior to epoxy underfill.

The test assembly used in this study was a Flip Chip Technologies laminate board, part number FB250-PCB, 10 pads for the FB250 flip-chip silicon nitride passivated die. These die feature 48 peripheral eutectic solder bumps at a 0.6mm pitch.

Test Components

The test components were assembled using a controlled process. FB250 die were first placed bumps-down into a 0.0015-inch -thick bed of flux to deposit a controlled amount of liquid flux onto each solder bump.

The die was placed onto the substrate and reflow soldered using a five-zone reflow furnace with a peak temperature of 230°C. Two sets of soldered assemblies were set aside as control units. The remaining soldered assemblies were cleaned using the HFC-based formulation.

After cleaning, the test assemblies were then warmed to 90°C and underfilled using a high-performance underfill. The underfill employed is an epoxy-based, low-stress material for use on semi-rigid and flexible substrate materials with component gaps as low as 20 µm.

The underfill was cured for 30 minutes at 165°C in a forced air oven and then evaluated for evidence of flow-induced voids, filler striations and incomplete fillets, employing a scanning acoustic microscope equipped with a 100MHz transducer.

JEDEC Preconditioning

The parts were then subjected to JEDEC level-3 preconditioning, consisting of unbiased environmental soak for 192 hours at 30°C and 60% RH, followed by three passes through a reflow process with a peak temperature of 240°C ± 5°C. The assemblies were again evaluated by acoustic microscopy for evidence of delamination and cracks (Figure 2).

Finally, the parts were subjected to pressure cooker accelerated testing at 121°C, 100% RH, and 2.2 atmospheres of pressure for 48 hours. The assemblies were again evaluated by acoustic microscopy for evidence of delamination and cracks. The results are shown in the table.

Summary

Flip-chip devices enable higher performance and higher I/O, with the potential for thousands of bumps under the die. However, in the production of flip-chip devices, flux residue is known to decrease reliability. To adequately clean under flip-chip requires a cleaning agent with low viscosity, low surface tension and soil solubility which is easily rinsed and offers residue-free drying.

This demanding cleaning requirement favors vapor phase cleaning technology. HFC-43-10mee is the building block toward formulating a viable flip-chip-cleaning agent and can be blended with other materials to provide the desired properties.

Acknowledgements

The authors acknowledge Michael Todd and his staff at Dexter Electronic Materials for assembling and testing flip-chip assemblies, and others who assisted in preparing and processing samples employed in the experiments.

References

1. Peter Elenius, "Flip Chip Burning for IC Packaging Contractors," FCT, 1998: In the paper it is stated in that the compounded annual growth rate for 1999 & 2000 is 49.6%. at this rate the market for flip chips in five years will be 500-1000% larger than it is today.

2. M. Todd and M. Bixenman, "The Effects of Post-Reflow Cleaning Processes on the Performance of Flip-Chip Devices," Proc. of APEX 2000, Long Beach, Calif.

3. M. Bixenman and E. Miller, "Cleaning Issues Related to Flip-Chip, Ball Grid Array and Chip-Scale Pack-ages," Proc. of APEX 2000, Long Beach, Calif.