I recently returned from a full week at the International Test Conference (ITC) in Atlantic City, N.J. Much of the year's focus was on DFT (design for test), BIST (built-in self-test) and other strategies that promise to help make the next generation of SOCs (systems-on-a-chip) testable. Of course, there was a fair amount of tester hardware there, too. One large test equipment company, whose name the editor prohibited me from including here (hint: it begins with a "C" and is headquartered in Fremont) rented the Trump Taj Mahal stage for a show that headlined Sinbad, the comedian. Sinbad took a straight shot at us test folks with the line, "What? It's BAD? I don't know. We just test 'em. It was good when it left here!" Painful Snapshot So, how does this all tie together? Sinbad evoked a painfully correct snapshot of the test community infrastructure. I've commented previously that there is a huge imbalance of resources between design and test. The result is that there is a huge struggle in most companies to produce adequate test programs at all, let alone adding a lot of refinement to the process of testing mixed signal and complex logic devices. Folks who are struggling just to keep on doing things the way they've been doing them are having (and will continue to have) trouble assimilating the new DFT and BIST techniques. This is due to both capacity and what I will call an "educational gap." Papers and oratories on DFT tend to fall into two categories: One is a high-level discussion about the basic concept, deployment strategy and wonderful benefits of DFT. These are the kinds of presentations that vice presidents and CEOs like to hear because it makes them feel that if they could just "get those slugs that insist on tester purchases to adopt this new technology" they could eliminate a lot of their capital budget. These talks give almost no data useful to actual working engineers.
The second category is one that is potentially useful-if we could only understand it! This is the talk presented by some Ph.D. who has devoted his/her life to DFT studies and verification. When this Einstein of the nether world between the design and the DFT arena speaks, he is hard to understand. This is because much of the hard core information is delivered at a level of mathematics and logic above that of the installed base of test engineers. I would venture to say that it requires a special educational focus. To put it another way, the industry has been able to fill a large majority of the test engineering spots with bachelor-degree-equivalent engineers. In my opinion, DFT adoption is pushing the bar up to a master's or Ph.D. level for basic competence. Before a lot of you who don't have master's or Ph.D. degrees start lynching me, remember that the previous sentence said "level of competence," which one could acquire in a number of ways. Any way you look at it, the pool of candidates is smaller and the time to grow them is longer. 'We Just Design 'Em' In addition, these folks are going to have to be dispersed through the whole process from design to manufacturing. After all, "We just design 'em" is no better than "We just test 'em." So, start stocking up on the new kind of CSP for the test arena, the "Certified Smart Person." Your boss has, by now, read the ITC abstracts and wants you to put DFT into the flow and take out more test capital. There are only so many Certified Smart Persons around, so you had better get started now. But, hey, if you need help putting a recruiting party together, remember, we have that technology nailed!
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