PATENT NUMBER: 6,072,236 ASSIGNEE: Micron Technology Inc. INVENTOR: Salman Akram, David Hembree and Warren Farnworth TITLE: Micro-Machined Chip-Scale Package (While this patent refers to a chip-scale package, the process is performed at the wafer level, and today it would be called a wafer-level package.) The process begins with a typical memory wafer with a passivation layer of silicon nitride, silicon dioxide or spin-on-glass. A blank silicon wafer has holes anisotropically etched corresponding to the pads on the memory wafer. This process forms holes with a tapered 54-degree angle. The blank wafer is aligned to the memory wafer and bonded to it using boron phosphorus silicate glass (BPSG), epoxy or polyimide. Surface Passivation The entire surface is passivated with silicon nitride using a plasma-enhanced chemical vapor deposition (PECVD) process. The pad areas are then opened to establish contact to the pads, which can be accomplished either by wire bonding or metal deposition. While electroless copper can be plated on the pads, a better approach is to deposit a Cr/Cu layer over the wafer and then remove it from the surface using either a masking process or chemical mechanical polishing (CMP). High-lead solder paste can be screen-printed into the holes and then reflowed to form the solder bumps shown in the figure. Due to the support provided by the tapered walls, the solder connection should be very rugged. Alternatively, instead of using solder to form bumps, they can be formed by electroless plating. The bump contacts can then be connected to a TAB frame. Bumps can also be formed using other methods. While silicon is the preferred substrate, other substrates that match the TCE of silicon, such as mullite and cordierite, can also be used. Once the wafer is bumped, the die are electrically tested and burned-in prior to being separated into individual packages.
Other Capabilities Although not shown in the figure, this approach can also be employed to redistribute the I/O pads on the basic memory die. A redistribution layer can be formed on the surface of the memory die and the holes in the micro-machined substrate can be formed to match the new pad locations. A number of different redistribution approaches are described. The backside of the micro-machined substrate can be metallized, or some type of intermediate interconnect structure, like a TAB frame, can be placed between the two silicon slabs. The TAB frame can be bonded to the memory die and holes in the silicon can be opened to make contact with the redistributed pads on the TAB frame. In addition to the formation of through-holes for making the I/O connections, trenches can also be etched in the silicon substrate. Trenches are shallow, parallel paths etched in the silicon to aid in the alignment of the chip to a connector for vertical stacking devices (in the arrangement shown). Trenches can also be used to connect multiple bond pads, and bumps can be formed anywhere along the trench length.
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