Who hasn't experienced the frustration of searching for the defective bulb in a string of Christmas tree lights? Finding that single bulb among dozens of innocent bystanders is a challenge, since one bulb in the series will darken them all. The situation is worse for the mega-strings with hundreds of bulbs. Times were easier when we were happy with a few quaintly colored bulbs wired in parallel. The offending bulb is found instantly-it's the one not lit! The problem with series circuits (as well as serial processing) is that one defect in the string brings down the whole show. The task of failure analysis involves sorting through each element in the string. That's where the all ure of parallel processing comes in: The elements are made and tested individually before selecting good units for final assembly. Defects are found earlier and with less effort. Increasing Complexity With increasing process complexity at less than perfect yield, there is some logic to breaking the process into segments that can be processed and tested in parallel. In addition to higher yields and faster cycles of learning, parallel processing can cut total process times by fabricating elements simultaneously. Does a light go on? Parallel processing is particularly attractive for wafer-level packaging of complex ICs; fabricating a low-yielding package onto an expensive wafer is not viable in our hotly competitive IC industry. It is better to fabricate a wafer-sized package, and then test it before assembling the package to the wafer. Only high-yielding packages are used, while the rejects are failure-analyzed to drive process learning. Although parallel processing is not necessary-maybe even meaningless-for simple flip-chips, such an approach is attractive for increasingly complex packages. For example, packages involving power, ground and intra-chip wiring could be fabricated and yielded before assembly to an expensive wafer.
Beginning with small flip-chips, the industry is advancing toward wafer-level packaging of ICs-which are growing more complex almost daily-driven by cost, logistics and performance. Considerable global development efforts are aimed at squeezing more interconnections into the package. Driven by increasing complexity, IC manufacturers are considering parallel processing of wafer-level packaging more seriously. Power and ground distribution for high- performance ICs is an early and obvious wafer-level application. Several parallel processing technologies have emerged from the laboratory, and more are in the wings. The Tessera (San Jose) WAVE process has demonstrated the capability of packaging high-I/O chips at the wafer-level [tessera.com]. In the WAVE process, several layers of interconnection are fabricated on a tensioned pellicle that can be tested and yielded separately. Later, the good pellicles are joined to wafers to form wafer-level packaged ICs. Recently, TruSi (Sunnyvale, Calif.) demonstrated MEMS processing to fabricate 200 mm diameter packages that can be assembled to IC wafers in a parallel process [trusi.com]. While these technologies are at an early stage, they illustrate the potential for parallel processing to enable wafer-level packaging of complex multilayer interconnections. IC manufacturers everywhere are developing wafer-level packaging technology for complex devices and are exploring multilayer packages that are enabled by parallel processing. Processing and joining technologies are being adapted from MEMS processes already in volume production for IC sensors. The move from laboratory to production can occur rapidly for approaches that utilize the existing infrastructure. This is an area to watch closely.
|
