Scientists from Lucent's Bell Labs Claim 'World's Smallest Transistor' Murray Hill, N.J.-Scientists from Lucent Technologies' Bell Labs have fabricated what they claim is the "world's smallest transistor." The invention, the "nanotransistor," is an individually addressable transistor whose channel consists of just one molecule. Each measures one billionth of a meter. At that size, according to Bell Labs, about 10 million would fit on the head of a pin. The nanotransistors, which are about one nm in size, appear to rival silicon transistors in performance. They are produced with a class of organic semiconductor material known as thiols, which contain hydrogen and sulfur in addition to carbon. A few months earlier, the same Bell Labs researchers, Hendrik Schon, Zhenan Bao and Hong Meng, unveiled a transistor with a single-molecule channel length. That transistor could only be produced as a matrix of a few thousand molecules that worked in tandem. Now the team has succeeded in fabricating molecular-scale devices that can be controlled individually. Bell Labs said the main challenges in making nanotransistors involved fabricating electrodes that are separated by only a few molecules, and attaching electrical contacts to the tiny devices. The scientists answer was to carve a notch into a Si wafer and deposit a layer of gold at the bottom to function as one of the transistor's three electrodes. They then dipped the wafer into a mixture of thiol molecules and some inert organic molecules and let it dry. As the solution evaporated, it formed a film exactly one molecule thick on the electrode. By adjusting the ratio of thiol to the inert molecules, the researchers were able to ensure that just one active molecule was present in the area on top of the gold electrode. Researchers then deposited another gold electrode on top of this film, while building the transistor's third electrode on one side of the Si notch. [lucent.com]
Motorola Discloses Plans for III-V-on-Silicon Technology By Terry Thompson, Editor-at-Large Austin, Texas-A Motorola Labs' discovery, which enables GaAs, InP and other very high-performance, light-emitting compounds to be grown on silicon substrates, will be commercialized by Thoughtbeam, a new Motorola subsidiary. Until now, Motorola noted, it was impossible, due to a fundamental material mismatch, to grow III-V materials on silicon substrates. Motorola's solution was the introduction of an intermediate layer of material between the silicon and the III-V material. Padmasree Warrior has been named general manager and corporate vice president of Thoughtbeam. Earlier, she was chief technology officer and director of central R&D for the company's Semiconductor Products Sector. Warrior told Chip Scale Review, "The cost of GaAs-on-silicon wafers should be somewhere between epitaxial silicon and GaAs wafers at the 150 mm size. "We can, of course, place GaAs and other compounds on any size wafer so that the existing fab, assembly and packaging infrastructure can be used-a significant advantage for users. Existing processes and equipment will work, and there is no need for new CAD tools to develop news chips." Designers will obviously make some changes to take advantage of the new capabilities, she added.
Selective Deposition of GaAs "We're also looking at some ways to selectively deposit GaAs on top of fabricated silicon devices. Motorola does not make its roadmap available, but you should see GaAs-on-silicon devices from Motorola late next year. As we proceed, there will be additional hetero-compound mixed material announcements." Warrior notes that the technology offers the potential to benefit multiple industries, from semiconductors to communications to optoelectronics, and "we will license it broadly." To ensure that a supply of GaAs-on-silicon wafers is available to potential customers for their internal evaluation, "we have authorized our vendor, IQE, to produce and supply GaAs-on-silicon wafers for our evaluation program." IQE anticipates supplying evaluation wafers in the first half of 2002. The Motorola technology can reportedly provide large, affordable III-V on silicon wafers at a fraction of the cost of pure GaAs wafers. The process integrates superior III-V material, optical and electrical performance with mature silicon technology. The result is improved cost effectiveness for higher-performance optical device applications. Additionally, Motorola's process will enable photonics integration with microelectronics on a chip. Since silicon is more robust than GaAs, breakage issues are not a factor and the thermal conductivity of GaAs-on-silicon is superior to pure GaAs. Evaluation Program The evaluation program should accelerate the industry learning curve for GaAs-on-silicon. The program also may enable potential customers to assess the technology and gather their own information as a precursor to target new designs, remap existing products and explore other new options. Developed by Motorola Labs, GaAs-on-silicon combines the best properties of workhorse silicon with the speed and optical capabilities of high-performance III-V material compound semiconductors. The GaAs-on-silicon technology will permit significantly less expensive optical communications, high-frequency radio devices and high-speed microprocessor-based subsystems by eliminating the current cost barriers holding back many advanced applications. The technology will change the economics and accelerate development of new applications, such as broadband fiber to the home, streaming video to cell phones and automotive collision avoidance systems. [motorola.com] STATS Ramping Test Services with New $20M Milpitas Site By Ron Iscoff, Editor Milpitas, Calif.-Singapore's ST Assembly Test Services (STATS) has beefed up its already impressive final test offerings with the opening of FastRamp Test Services Inc. STATS says that it will invest $20 million in the wholly owned subsidiary. Of the total amount, some $10 million is for buying next-generation ATE. The other half will be used for remodeling an existing building and for transferring some test equipment to Milpitas from Singapore. Located at 1768 McCandless Drive in an existing 34,000-square-foot building, FastRamp is slated to open this month. The company's Silicon Valley Test Development Center, now operating in San Jose, will move into the Milpitas building. STATS' sales office, now at 1450 McCandless Dr., will also move into the new Silicon Valley flagship location. FastRamp's ATE portfolio will include Teradyne's Catalyst, J750 and Tiger, Agi-lent's 93K and Credence Systems' Quartet. Mark Kelley has been promoted to General Manager of FastRamp. Kelley was most recently ChipPAC's director of Asian test operations. He joined STATS last February as manager of technical programs. According to STATS, the company wants to offer "a microcosm of our elite-class test facilities in Singapore" with a similarly designed and comprehensive array of advanced test platforms, handlers, probers, interface hardware and manufacturing processes. [statsus.com]
Intel Researchers Develop New Transistor Type, Claim Improved Speed, Efficiency and Less Heat Santa Clara, Calif.-Intel Researchers have developed the TeraHertz transistor, which contains an innovative transistor structure and new materials that will offer a "dramatic improvement" in transistor speed, power efficiency and heat reduction. The company termed the development an "important milestone" in the effort to keep the pace of Moore's Law and to remove the technical barriers that the semiconductor industry has only recently began to identify. Gerald Marcyk, Intel Labs' director of components research, said, "Our goal is to overcome these barriers and produce chips that have 25 times the number of transistors of today's microprocessors at 10 times the speed, with no increase in power consumption." Researchers were slated to discuss details of the new transistor structure at December's International Electron Device Meeting in Washington, D.C. The IEDM meeting is often used as a launching pad for important technology announcements by IDMs. New Transistor, New Material Intel is calling the new transistor a "depleted substrate transistor." A new material, called a "high-k gate dielectric," is part of the company's new technology. The depleted substrate transistor is a new type of CMOS device where the transistor is built in an ultrathin layer of Si on top of an embedded insulation layer. This ultra-thin layer of Si is different from conventional SOI devices, and is fully depleted to create maximum drive current when the transistor is turned on-enabling the transistor to switch on and off faster. When the transistor is turned off, however, unwanted current leakage is reduced to a minimum level by the thin insulating layer. This layer enables the depleted substrate transistor to have 100x less leakage than traditional SOI schemes. Low-resistance contacts have been employed on top of the Si layer of the depleted substrate transistor. Another key element, according to Intel, is the development of a new material that replaces Si02 on the wafer. This high-k gate dielectric reduces gate leakage by more than 10,000x, compared to silicon dioxide. [intel.com]
August Technology: Bump Inspection System Minneapolis, Minn.ÑAugust Technology has received its first follow-on order for the 3Di-8000 wafer and bump inspection system for an undisclosed semiconductor maker. The system is scheduled to be installed in the U.S. before mid-year. [augusttech.com] Kulicke & Soffa Industries: Ball Bonders to SPIL Willow Grove, Pa.ÑKulicke & Soffa Industries announced that Silicon Precision Industries Ltd. (SPIL) has placed orders for 166 Model 8020-PPS ball bonders. The machines will be employed to assemble fine-pitch BGA packages. [kns.com] Micro Component Technology: Tapestry Test Systems St. Paul, Minn.ÑMicro Component Technology has received a follow-on order for a Tapestry strip test handling system. The company says the order brought total Tapestry bookings to about $1 million over a recent 30-day period. [mct.com] |
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