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Semiconductor Heavyweights Are Preparing Wafer-Level Game Plan
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Dr. Tom Di Stefano Senior Contributing Editor |
When the big guys show up on the playing field, the small fry head for the bleachers to watch the game from a safe distance.
After all, there's no sense in getting bruises and broken bones if you're not in the game. The same dynamics apply to wafer-level packaging, where the turf is increasingly dominated by the chip makers. Truly, WLP is becoming a game for the heavyweights.
As WLP devices reach the market, a picture is emerging in which semiconductor makers are supplying the technology used to package their IC products.
Of the two dozen wafer-level product lines already introduced, only a few are based on technologies outside the reach of semiconductor manufacturers.
In preseason practice rounds, merchant market technologies played a role in sample production and licensing deals. But now, as the heavyweights suit up for the game, the trend is toward direct participation by the semiconductor fabs and their labs.
Wafer-level production first appeared in low-I/O chips, where simple bumping processes are adequate, and requirements for redistribution are minimal.
Flip Chip Technologies, Phoenix, Ariz., and Unitive Semiconductor, Triangle Research Park, N.C., with roots going back to semicon-ductor technologies, are serious players.
More Resources
With increasing complexity and higher volume, the resources needed to compete are ratcheting upward. Consider that recent announcements in the field have come mostly from the semiconductor sector.
WLP fits the mindset of chip makers because its production incorporates complex processing and redistribution layers that demand semiconductor defect learning discipline. Multilayer redistribution wiring is more like wafer processing than package assembly-a distinction that will sharpen with advances in complexity.
Perhaps the greatest benefit of WLP derives from factors beyond package cost, and has more to do with integration of the backend into the fab.
Learning Cycles
Efficient logistics flow and faster learning cycles are enabled by a paradigm in which the product is complete when the wafer is diced. The eventual integration of burn-in and final test into the wafer flow provides further efficiencies. These benefits, along with others that are less obvious, are lost if the flow is broken to ship wafers out to a packaging foundry.
The rationale for shipping wafers offshore for packaging is evaporating. Furthermore, the know-how and process technologies of WLP are rooted in wafer fabrication.
Freed from the need for low-cost labor and assembly expertise, IC suppliers are expected to pull WLP closer to their fabs.
This game is being played out differently from the CSP bandwagon, with its plethora of variants accompanied by cheerleading hyperbole.
The IC suppliers are driving WLP, shaped by their product needs and strategic roadmaps. In targeting internal needs, semiconductor makers are protecting their investments with secrecy, rather than publicizing their programs prematurely. We will see it when they are ready to call the play.
We expect the IC suppliers and semiconductor makers to take the lead. Strategic development is being pursued around the world by corporate laboratories quietly accumulating intellectual property positions.
Wafer-level technologies will be an important part of the semiconductor industry for decades, and, unlike package assembly, merit significant investment.
Solutions are being shaped by complex issues including IC performance, logistics, test strategy and total system cost in ways that merchant IC packagers could not achieve in isolation.
Correspondingly, we expect WLP to be pulled closely into the orbit of the wafer fabs, where chips will be designed and wafers fabricated with packaging issues playing a significant part.
This is a new game, one that will reshape the IC packaging industry. Should we all hit the showers and go home as the semiconductor fabs take over? Not at all! First, WLP will impact only selected sectors of the IC market, while others continue in business as usual.
Second and more importantly, WLP opens up high-value opportunities in electronics assembly.
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Dr. Di Stefano is president of Decision Track Inc., San Jose, and an internationally recognized expert on CSPs and wafer-level packaging. [tomd@decisiontrack.com]
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