To meet that demand, probe cards and wafer probing systems must be able to handle high probe card forces without deflection of the wafer being tested. Tool Requirements In addition to changes in probe card technology, wafer probing systems must incorporate the latest state-of-the-art hardware and software technologies, as noted below, to truly deliver value. Wafer Transport Advanced automatic wafer probing requires an accurate and reliable method of moving wafers from a cassette to the prober chuck top. Profiling Prior to Testing Wafer profiling is a critical function with two basic purposes: one is to find the thickness of the wafer so that consistent probe pressure is provided during probing of the wafer; the second is to locate the center of the wafer with respect to the center of the chuck, which allows the prober to pinpoint the exact position of the device to be tested. Alignment Alignment is a complex process in which a previously stored vision target on a die can be located by a prober. The prober then finds that target on a subsequent wafer and locates it again on other die that are a chosen number of strategic die locations away. (Figure 5 depicts probe mark accuracy.)
Throughput Throughput is one of the biggest factors in lowering the cost of test. Typically measured in wafers per hour, throughput can be influenced by any one of numerous activities that occur in the test cell. These include wafer profiling, transfer in and out of the cassette, reading the wafer ID, wafer alignment, moving the wafer to and from the chuck top, die to die stepping time and the actual time to perform the electrical tests on the device. Probing Force on the Wafer To achieve the required electrical contact of the probe card pins to the bond pads on a device, the wafer prober must move the wafer with enough force to slightly compress the probe card pins. Today's probers offer a vertical force from 18.4kg to 150kg with little deflection of the chuck top. Devices with a high number of contacts require higher forces and lower deflection. Multi-Die Testing Parallelism, with respect to probing, represents the number of die that can be tested at the same time by a multi-die probe card. Current cards can probe from four die up to 204 die at once. The advantages of multi-die probing are extremely high throughput and significantly lower test costs.
Software Platform Very complex software algorithms are needed to keep wafer probers user-friendly while still meeting chipmakers' needs for high accuracy, reliability, throughput and control. Future Directions in Probing Those features referenced earlier are all part of today's systems in one form or another. The future of semiconductor manufacturing, however, is certain to require additional changes to the test cell, each of which will have its own specific challenges. 300mm Probing The size of 300mm wafers presents a unique challenge to system vendors, because the weight and rigidity of the chuck must be increased to accommodate the larger size of the wafers and the rigidity needed to support massively high parallel testing. At the same time, customers want to be able to use their probers on products that are not tested in parallel and instead demand high-speed movement from die to die. That means equipment makers must offer probers robust enough to withstand high loads and agile enough to move quickly, with the supreme accuracy and alignment required by the tight geometries of 300mm chips. Fiducial Alignment As mentioned, device geometries are shrinking very quickly, driving the device I/Os and probe card pins to extremely small sizes and pitches. A new technology that addresses these small features is "Fiducial Alignment," which enables the accurate matching of pins to device bond pads without requiring the system to see the probe card pins. This is accomplished by placing a fiducial mark, which has a known position to each probe card pin, on the probe card. The wafer prober then locates the fiducial mark and downloads the known pin locations, allowing the exact location of each probe card pin to be identified for fast, accurate alignment. Test Cell Automation The next major advance in prober technology will be automation, which will allow a wafer prober to be loaded with an unknown wafer and automatically perform a complete setup and test. This is close to reality today, as some advanced manufacturing sites have implemented various forms of automation, but true automation is a complex system of information gathering, processing, analyzing and real-time control between every aspect of the test cell. Fortunately, leading automation companies are already working on solutions that will build out the required communications, including the ability to store, statistically analyze and process corrective actions in real time from a server to the test cell equipment. Chip-Scale Packages As the trend toward CSPs such as flip chips and wafer-level packages grows, resulting in more bump applications, chipmakers will require advanced technologies for determining the height and location of the bumps to accurately probe them. Accuracy will also become paramount for non-bump applications, since bond-pad pitches are decreasing rapidly and system accuracy is becoming critical. Conclusion Whatever changes the future holds for semiconductor manufacturing, wafer probing, in particular, will be a critical component in the test cell on the manufacturing test and packaging floors. The ability to probe devices accurately and reliability before and after they are packaged has become imperative for chipmakers with the need to lower the cost of test, even as they adopt new technologies.
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