By Dr. Nadia Yala, Jan Danvir, Jing Qi, Dr. Prasanna Kulkarni and Marc Chason, Motorola Inc., Schaumburg, Illinois
Many industry forecasters predict a sharp rise in the use of flip-chip packaging.(1,2) The technology drivers include increasing I/O demands and higher speed requirements. The manufacturing drawbacks of flip chip are well recognized.(3,4) Traditional flip-chip assembly on the surface-mount line is inefficient, since non-standard processes are employed. Placing and soldering flip chips is generally not problematic; it is the capillary flow underfill step that poses concern. The nature of capillary flow underfill simply does not fit well in the ideal SMT process flow. New and expensive dispense cells are required that consume valuable floorspace, and expertise is needed to keep the process running smoothly without sacrificing cycle time or pulse rate. These underfills are cured in yet another process step, requiring more equipment and floorspace. Once cured, the IC is permanently bonded to the PWB, making repair difficult or impossible. Accordingly, the use of flip chip directly on expensive product PWBs has been restricted to products that absolutely require the performance enhancement of flip chip. Although the use of flip chip in packaged IC solutions has fared better, many of the same considerations apply. Improvements in Underfill Materials While many improvements in underfill materials over the last decade have considerably enhanced the manufacturing process, the most promising answer to an efficient SMT line is to apply the underfill to the die at the wafer level, moving all underfill handling and processing steps to the IC manufacturer or assembler. Moving to the wafer level enables the most cost-effective processing, since underfill is applied to hundreds or thousands of die at once instead of individually. The process creates a self-contained component that can be loaded into tape and reel and handled as any other surface mount part. In the ultimate implementation, the coated die is placed on PWB with standard pick-and-place equipment. No pre-fluxing is needed, since the underfill offers inherent fluxing properties. The underfill cures during reflow, and may even be reworkable, and no additional processing steps outside of the normal SMT process are required.(5) These advantages apply to both IC assemblers and SMT assemblers. Early Efforts Work has been in progress since the mid to late 1990s to develop wafer-applied underfills, with several segments of the industry involved.
Some of the significant players are Aguila Technologies, IBM, Jabil Circuit, Loctite, Motorola, National Starch and Chemical, 3M, Delphi and Japanese suppliers such as Fujitsu and Toshiba. Some of the earliest work was completed through a SEMATECH initiative, with the Georgia Institute of Technology performing exploratory work on a flip-chip process that would be "transparent" to the SMT line.(6,7) Motorola was a key consultant in this effort, which examined wafer coating and dicing processes and completed some preliminary, limited work on assembly. Near the conclusion of the SEMATECH effort, Georgia Tech joined with partners in a NIST-ATP program to further develop the concepts, with efforts focused on thermoplastic materials.(8) Aguila Technologies has been working to address the shortcomings of current rapid flow and no-flow underfill technologies.(9,10) One result has been the methodology for providing pre-encapsulation on-wafer before dicing. This article outlines several research and development efforts seen in the industry in recent years. Wafer-Level Technologies Pre-applied underfills can be applied to the wafer or to single die, and may include substrate application as well. The underfill can be applied as a liquid or solid and may be thermoplastic or thermoset, filled or unfilled (Figure 1). The strategies being explored for wafer-level underfill can be divided into single material and multiple liquid material systems which are coated or printed in the liquid stage and then solidified or laminated as a film. Single material system is the most desirable, since it can minimize production processing costs. The single-component material must have fluxing properties initially, but be convertible to an inert underfill during reflow.(11) The single component material can be built upon epoxy-based, no-flow underfills since flux agents such as carboxylic acids can also serve as hardeners. These systems are not filled. The chemistry already permits curing within reflow, possibly followed by a post-reflow bake to complete the cure. A similar strategy may also be taken with a thermoplastic material.(12,13,14) Multiple Material Systems The primary multiple material systems consist of separate fluxing and underfill layers.(15,16,17) Material development is not straightforward; new chemistries are needed that must perform their individual functions while being compatible with the other material. The materials may be thermoplastic or thermoset, or a combination of the two. In most cases, the underfill layer is filled to gain the CTE needed for reliability. The fluxing layer may completely coat the solid underfill layer, may be applied only on the bumps or it may be deposited on the substrate. The fluxing layer contains no filler to interfere with solder joint formation, a problem discovered with early version of no-flow underfills.18 This layer must melt or liquify, coat and clean the surfaces to be bonded, deactivate and convert to a cured solid. The underfill layer may also melt or liquefy and flow to completely underfill the chip without interfering with solder joint formation, then convert to a cured solid, all within the few minutes of the reflow cycle. Film Adhesive System Adhesive films may also be applied to the wafer, generally using some version of a laminating process to adhere the film to the wafer. A liquid material is used to conform to the interface between the film on the die and the substrate, which solidifies to form the bond. Several researchers have proposed the use of these adhesive films to form the underfill layer at the chip side, coupled with the use of a fluxing layer on the substrate side, which may be pre-applied to the chip or to the substrate.(19,20,21) Technology Challenges Implementing wafer-applied flip-chip technology on a conventional SMT assembly line requires solving a number of technical challenges. A few challenges: 1. Development of a coating process for application of material to wafer 2. Bumping the wafer either before or after material application 3. Singulation of coated die from the wafer after material application 4. Alignment of coated die with covered or partially exposed bumps 5. Tack consideration to hold the coated die in place during reflow General strategies for the development of these materials and processes have been developed and are discussed in this paper. |
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