Wafer Coating The new underfill may be applied to the wafer either before or after solder bumping. Each approach offers advantages and disadvantages, and the most cost-effective approach will depend on the complexity of the resulting process. The demands on an application process prior to bumping are low. However, several researchers such as Aguila have described the coating process prior to bumping.(22,23,24) The advantage of this approach is that a flat, level of underfill layer can easily be achieved using mature processes such as spin coating. Openings are then formed in the coating using laser drilling, and the openings are subsequently filled with solder or other conductive material. It may be a potential issue to consistently fill the openings with solder in an efficient manner. IBM has also described a similar approach.(25) Producing a uniform consistent coating on a bumped wafer presents a greater challenge. The coating height relative to the bump height must be controlled, and the process will need adjustment for different bump and pitch configurations. After coating, the underfill is B-staged (liquid material systems) to produce a tack-free surface compatible with die loading into tape and reel for shipping, storage and automated pick-and-place The Motorola, Loctite and Auburn University Consortium and the National Starch Consortium have proposed processes where the wafer is coated after bumping. The Motorola, Loctite and Auburn University Consortium has developed a material suitable for the processing of wafer-applied underfill. The coating process is performed after dicing (Figure 2). This technique also enabled them to eliminate any potential issues associated with exposing uncured epoxy to water used in the cooling system of the saw blade.(26) The National Starch Consortium coating process takes place after bumping but prior to dicing, placing a greater demand on the material and its ability to withstand localized heat and moisture. The consortium has concentrated on development of a screen printing process for coating the wafers, with extensive experimentation done to explore a suitable rheology. Both thermosets and thermoplastics were examined, in the filled and unfilled states, using a variety of the usual screen printing variables.27 A detailed analysis of the mechanics of screen printing and its implications on coating quality was also performed.(28) Another alternative is to completely cover the wafer in underfill, then planarize the structure by grinding or polishing to expose the bump tips after B-staging.(29,30) One additional issue to address is wafer sawing. The compatibility of uncured underfill with water is a concern. In addition, the presence of coating in the saw streets may result in saw blade failure.31,32 Applying Underfill as a Film The coating process may also be simplified by applying the underfill as a thick, solid film.(33) The underfill film may also be applied to the wafer before or after solder bumping. For unbumped wafers, apertures for bumps in the film are formed either by photo lithography or by laser drilling. Laser drilling has been developed by the high-density interconnect industry for microvia formation, and should be easily transferable to this new application. The apertures are subsequently filled with solder or other conductive material using printing, jetting, electroless plating, etc.(34) For a bumped wafer, the underfill film is laminated with one of the techniques mentioned earlier, and the wafer is processed further to expose the solder bumps (Figure 3). 3M has developed a solvent-assisted polishing process that removes the thin film of underfill coating the bumps without damaging the bumps or the underfill surface.(35) No researchers to date have been able to devise the simple, single-stage application approaches that are described in the patent literature. Some of the coating methods explained in this section utilize standard industry processes and equipment, while others rely on completely new systems to apply the underfill to the wafer. The lowest conversion cost process that delivers the best solution to the SMT assembler will ultimately drive the industry solution.
Minimizing the SMT Burden Assembly of the pre-coated flip chips to the PWB is intended to minimize the burden on the SMT line, with the ultimate goal of a completely transparent flip-chip process (Figure 4). In reality, some level of adjustment to the process will likely be needed, but this can be minimized with an intelligently engineered process. At placement, the chip must be identified by the vision system. The solder bumps are used as fiducials, and the ability of the camera to recognize the bumps may be impaired by the presence of the surrounding underfill material. This consideration may impact the coating process selection, giving preference to a method that keeps the bumps as clear as possible, or the image of the bumps may be enhanced with alternative lighting schemes. Fortunately, many placement machines offer flexibility within their vision system to optimize the imaging. Parameters such as light intensity, illumination angle, etc., can be varied. Several researchers have shown success in imaging coated die.(36,37) Some method of tacking the chip in place at placement will be required, as the tack function normally supplied by flux is not present to adhere the chip as the assembly traverses conveyors into the reflow furnace. Tack may be achieved by heating the underfill material until it softens and becomes tacky. Recognizing the need for tack, both the Motorola and National Starch Consortiums developed material systems to soften with heat.
Another method to adhere the chip to the substrate during assembly is to dispense a fluxing underfill on the board prior to placing the chip.(38) While specific approaches, concepts, and general heating strategies for the tack development are being used, due to proprietary nature of these heating techniques the information is not being disclosed until intellectual property has been secured. Reflow Studies of Coated Die The relative liquefying points of the materials involved will be important for solder joint and fillet formation. The wettability of the underfills to the substrate material, including a variety of solder masks, will impact the final assembly results. Georgia Tech has performed symptomatic studies of the reflow of solder joints in the presence of pre-applied underfill.(39) Lab experiments discerned the sequence of material changes using a hot plate in conjunction with a high-speed camera to record the events. The hot plate was programmed with a simulated reflow profile. The experiments revealed softening temperature ranges, the fillet formation and solder collapse and wetting. Several failure mechanisms were observed. Two types of void formation were noted; one was attributed to incomplete contact between the underfill solid film and the substrate, although this occurrence was reduced by baking the chips prior to assembly. The second was a result of outgassing during the preheat portion of the profile. The outgassing increased to the point that solder joints were disrupted and eventually separated. Partial collapse of the solder was also noted, a result of underfill curing prior to complete wetting. This type of real time monitoring system can help to understand critical events during assembly reflow and enable further improvement in material development to demonstrate that robust solder interconnects in wafer-level flip chip assembly can be obtained. Concept Demonstration The concept demonstration of wafer-level processing of flip chip has been introduced at several recent conferences. Although several wafer-applied underfill strategies are being explored, most of the published work is concentrated around the two-layer system and adhesive films. Alpha Metals has proposed at least three approaches for constructing a ready-to-assemble flip-chip package:(40,41,42)
Alpha Metals performed its experiments using Type 1 and 2 approaches on a quartz chip. The chip was placed onto a copper disk, then processed through a reflow oven set at a typical soldering profile peaking at 220°C. Good fluxing action was reported. 3M introduced the application of the adhesive film to a wafer concept at the Wafer-Level Packaging Technology Work-shop 2001, and published recently about this achievement.(43) 3M adhesive underfill film incorporates thermoplastics as film formers, and filler for reduction of the CTE. The wafer applied underfill film is laminated onto the bumped wafer using reduced pressure and heat. The wafer is processed further to expose the bumps.(44) With this approach 3M is claiming that approximately 30 to 50% of the bump height is exposed. |
Copyright © 2003