Ready-to-Assemble Packages Aguila Technologies is pursuing a multilayer approach with one underfill layer on the chip and one flux layer on the substrate.(45) On the chip, a filled version of their cyanate ester bismaleimide epoxy resin46 is screen printed, cured and then laser drilled to form openings for solder bumps. Bumping is presently achieved with a stencil printing process using solder paste, although an in-situ, temporary stencil process is under consideration for fine-pitch devices. On the substrate side is Aguila's polymer flux formulation, dispensed in liquid form. Aguila reports that it may be possible to use any no-flow polymer flux. After placement and reflow, a post-cure is needed, although this is targeted for elimination. Early assemblies survived as many as 7170 cycles in liquid-to-liquid thermal shock at -40°C to +125°C. The Motorola, Loctite and Auburn University Consortium has adopted a multilayer structure. Formulating a single material to perform all the underfill functions of a commercial product, including fluxing, reliable underfill and reworkability, was deemed too difficult in a reasonable time frame.(47) Experiments performed by that consortium used a two-layer coating process. The process consisted of a fluxing underfill screen printed on the bumps, followed by a bulk dielectric layer stencil printed on the wafer exclusive of the bumps. Each layer is B-staged after printing. The consortium reported on numerous aspects of the coating process. The significance of coating thickness on the final assembly results showed that only an optimal coating thickness will completely fill the gap between the chip and the board without interfering with solder-joint formation. Thicker or thinner coating might result in either unreliable solder joints or no solder joints at all.(48,49) 3M and Delphi reported on wafer-applied underfill film application.(50) For assembly, a fluxing material is dispensed onboard. Good solder joints are formed, and the reliability of these wafer-applied adhesives has survived over 1000 cycles from -50°C to 150°C (80 min/cycle). Simulation Prediction National Semiconductor has completed simulation work that examined solder wetting in the presence of a polymeric underfill layer. Single bumps were modeled in three locations on the flip chip, and the final shape was calculated as a function of interfacial tension, underfill contact angle, chip weight and underfill coating thickness. As the interfacial tension increased, solder wetting decreased to a minor degree. More importantly, a contact angle of less than 60° is recommended for proper fillet formation (referring to the contact angle between the underfill and the substrate), and the researchers cite an underfill coating thickness of 60% to 70% of the bump height as optimal.(51) Working within the Motorola NIST-ATP consortium, Auburn University sought to predict the influence of pre-applied underfill volume and material properties on final flip-chip assembly results.(52) A single solder bump model was created that predicted final chip stand-off height, and this model was extended to a multi-bump version. Conclusion Numerous researchers have demonstrated the feasibility of wafer-applied underfills though a variety of approaches. Success has been reported using films applied both before and after bumping. These film techniques achieve soldered attachments with both separate and inherent fluxing approaches. Materials applied to the wafer in liquid form are also being developed, and these materials provide fluxing action with no separate fluxing step required. Models of joint formation in the presence of underfill and the attendant fillet formation have been used to guide some of this development work. The limited reliability data available is an indication of the immaturity of the processes, but the extremely promising results suggest that a viable, production-ready wafer-applied underfill system will be seen in the near future. Acknowledgements The authors thank Michael Schen for his continued project support and guidance. References 1. E.J. Vardaman, "Flip Chip Markets: Supply and Demand for Wafer Bumping," TechSearch International Inc., 2001. 2. M. Campbell, "European Packaging Roadmaps," Proc. APEX 2001, San Diego, January 2001. 3. D.R. Gamota, C.M. Melton, "Advanced Encapsulant Materials Systems for Flip-Chip-on-Board Assemblies" Proc. IEEE/CPMT Electronics Manu-facturing Technology Symposium, 1996. 4. M. Edwards, "Some Factors that Affect Perfor-mance of Capillary Flip Chip Underfills," Proc. International Symposium on Advanced Packaging Materials, 1998. 5. L. Crane, D. Gamota, et al., "Making Direct Chip Attach Transparent to Surface Mount Technology," Chip Scale Review, Sep-Oct 1999. 6. D. Baldwin, C. Johnson and S. Busch, Final Report SEMATECH Underfill and Interfacial Integrity Enhancement (UIIE) PTAB Primed Chip Assembly (PCA) Project, Georgia Institute of Tech-nology Center for Board Assembly Research, Packaging Research Center, March 1999. 7. C. Johnson, S. Busch, D. Baldwin, "Wafer-Scale Packaging Based on Underfill Applied at the Wafer Level for Low-Cost Flip Chip Processing," Proc. Electronic Component and Technology Conference, 1999, pp. 950-954. 8. NIST-ATP web site, http://jazz.nist.gov/atpcf/prjbriefs/ prjbrief.cfm?ProjectNumber=98-06-0030. 9. DARPA contract numbers DAAH01-98-R043, DAAH01-98-P-R018, and DAAH01-99-C-R004. 10. NASA contract number NAS5-97220 and NAS5-9915, BMDO contact number DASG-60-98-C-0059, and Navy SBIR contact number N00178-01-C-3035. 11. R. Pennisi, M. Papageorge, "Adhesive and Encapsulant Material with Fluxing Properties," U.S. Patent 5,128,746, July 7, 1992. 12. K. Gilleo, D. Blumel, "Flip Chip with Integrated Flux and Underfill," U. S. Patent 6,194,788 B1, Feb. 27, 2001. 13. Y. Yamaji, "Semiconductor Device for Face Down Bonding to a Mounting Substrate and a Method of Manufacturing the Same," U.S. Patent 5,925,936, July 20, 1999. 14. W. Wang, M. Peters, et al., "Flip Chip Pre-Assembly Underfill Process," U.S. Patent 6,168,972 B1, Jan.2, 2001. 15. M.A. Capote, Z. Zhou, X. Zhu, L. Zhou, "Semiconductor Flip-Chip Package and Method for the Fabrication Thereof," United States Patent 6,121,689, Sept. 19, 2000. 16. Gilleo and Blumel, op. cit. 17. Gilleo, and Blumel, "Flip Chip Having Integrated Mask and Underfill Providing Two-Stage Bump Formation," International Patent 01/20676 A1, March 22, 2001. 18. S.H. Shi and C.P. Wong, "Recent Advances in the Development of No-Flow Underfill Encap-sulants-a Practical Approach Towards the Actual Manufacturing Application," 1999 Electronic Com-ponents and Technology Conference, pp. 770-775. 19. M. Capote, X. Zhu, "Semiconductor Flip-Chip Assembly with Pre-Applied Encapsulating Layers," U.S. Patent 6,297,560 B1, October 2, 2001. 20. A. Chaudhuri, M.R. Walsh, et al., "On the Path to Nirvana: A Bullet-proof Underfill Process for Direct Chip Attach," Proc. International Workshop on Wafer-Level Packaging Technology, March, 2001. 21. S. Charles, et al., "Pre-applied Flip Chip Attachment", Proc. IMAPS 2001, Baltimore, 2001, pp. 178-183. 22. M.A. Capote, X. Zhu, "Semiconductor Flip-Chip Assembly with Pre-Applied Encapsulating Layers," United States Patent 6,297,560 B1, October 2, 2001. |
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