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 Publisher's Letter
Hello to 2003 - are you ready for the new year?

 Assembly Lines
Despite a recession, top 5 IC packaging foundries retained their 2001 rankings

 Opto-Electronically Speaking 
Researchers at IBM's Almaden research center making nanometer-scale circuits

 Harvey Miller's Notebook
Emerging interconnection technologies ready for future electronic markets

 Packaging Matters!
Squeezing profits back into packaging

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Dispensing for Area Array Devices: The Technology is Evolving into Tools Suitable for Larger, Higher I/O Die
Dispensing Equipment Vendor Directory

How Long Will Your Test Boards and Sockets Last?

Why Wafer Probing Is a Critical Technology for the Semiconductor Manufacturing Test Floor

Contact Resistance: a Potential Source of Problems

Overview of Wafer-Applied Underfill Activities: How to Turn Flip Chip's Drawback's into Benefits

 Tools & Technologies
Dual DUT Probe Card Allows at-Speed Test and more...

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Invention describes how to form wafer-level hermetic packages

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January - February 2003
The International Reference for Chip-Scale Electronics, Flip-Chip Technology, Optoelectronic Interconnection and Wafer-Level Packaging
Industry News
Nicholas Leonardi (left) welcomes Publisher Gene Selven to the December meeting in Phoenix. Jody Mahaffey is at center.

Chip Scale Review Sponsors Phoenix MEPTEC Meetings

Phoenix-Chip Scale Review will sponsor all meetings of the southwest regional chapter of MEPTEC through this year, Nicholas Leonardi, chapter co-chair and worldwide sales manager for Tiros Corp. announced recently.

Jody Mahaffey, JDM resources, will now coordinate local registration and handle marketing for the Phoenix-based chapter. Publisher Gene Selven was on hand at the December meeting to hear a presentation by Lee Smith of Tessera on the stacking of chip-scale packages. [meptec.org]

Edward S. Duh

Orient Semiconductor Electronics Plans to Increase Market Share with Current Customers

Editor's Note: Edward S. Duh was recently promoted to president of Orient Semiconductor Electronics Ltd., the firm founded by his father, Dr. Eugene Duh, on June 10, 1971. His mother, until recently, was chairwoman. Headquartered in Kaohsiung, Taiwan, OSE ranked in fifth place among IC packaging foundries in sales for 2001, according to the Semiconductor Technology Center. Chip Scale Review interviewed Mr. Duh recently in Milpitas, California.

Milpitas-Mindful that he's taken over the reins of the family business-a $200 million plus company-during the worst industry recession in history, OSE President Edward S. Duh is reflective beyond his young years.

Duh is contemplative-but enthusiastic-about the near-term prospects for growth. In addition to looking for new customers, Duh plans to increase OSE's market share with current customers. This, after all, he says, "is something we can control" apart from the economy.

Did he anticipate a recession that would run for two years? "Definitely not," he observes. "I think everybody in the industry experienced very good growth in the year 2000. We did not anticipate the recession continuing for this long."

It's been less than four years since OSE acquired majority ownership of the former IPAC, the San Jose-based packaging foundry, and renamed it OSE USA. Duh admits the company hasn't met expectations.

OSE USA, he says, is now focusing on front-end package development and small volume production. Among the goals for OSE USA is to pull the larger orders offshore to one of OSE's high-volume plants.

Duh views China as "an interesting place" he's visited several times, but is not ready to set up shop there yet. "Certainly there is a lot of demand in China for semi-conductors, but we're taking a conservative approach." He's following the demand on China's domestic market.

"Although a lot of electronic goods are assembled in China-which drives a lot of semiconductor devices-the majority are still imported. From my perspective, the market there is not yet mature."

While China is beckoning to many competitors, Duh points out that Taiwanese companies require their government's approval-something that could be slow in coming-before putting up bricks and mortar. - R.I. [ose.com.tw]

Dr. Wong Joins Lumenon Board

St. Laurent, Quebec, Canada-Lumenon Innovative Lightwave Technology Inc. has appointed Dr. C.P. Wong to its Tech-nology Advisory Board.

Dr. Wong is Regents Professor at the School of Materials Science and Engineering at Georgia Tech. [lumenon.com]

Japanese Companies Order SOI Bonders

Scharding, Austria-EV Group says it has shipped several EVG850 SOI wafer bonding systems to undisclosed Japan-based device makers. The orders include "several" 200mm systems and one 300mm system. [evgroup.com]

IBM's 200mm diameter transparent stack shows a fully processed circuit transferred onto glass.

3-D Chips: Up, Over, Stacked, Bipolar or CMOS?

By Terrence E. Thompson, Senior Editor

Yorktown Heights, N.Y.-IBM has demonstrated a technique for building 3-D ICs that increases performance, functionality and density.* The chips are assembled by bonding functional circuits from multiple wafers at the wafer level, and then interconnecting the layers.

Today, most chips are 2-D-with transistors in one plane-connected by multilayer conductors. Going 3-D increases performance, functionality and device-packing density. 3-D benefits include reduced wire length and increased bandwidth between logic and memory.

In a separate development, IBM researchers in East Fishkill, N.Y., created the world's fastest silicon-based transistor, a 350GHz SiGe bipolar IC. This device is nearly 300 percent faster than production devices, and is 65 percent faster than previously reported Si transistors.

In standard CMOS, electrons travel horizontally, so shortening the path requires a narrower transistor-an increasingly costly and difficult task. With bipolar transistors, electrons travel vertically, so the speed is improved by reducing transistor height, not width.

Vertical Profile Scaling Technique

IBM's novel vertical profile scaling technique shortens the electrical flow path to improve performance. IBM anticipates the new transistor will lead to communications chips with speeds of more than 150GHz in about two years. The transistor is also expected to result in substantially lower power consumption and lower cost for communications systems and other electronic products. [chips.ibm.com]

* See Chip Scale Review, November-December 2002, p. 15, "Intel Researchers Develop 3-D Transistor Design" for an up-and-over CMOS approach.

Zaid Ayoub
Nick Langston Sr.

Credence Systems Sells DCI Subsidiary, Buys Optonics Inc.

Fremont, Calif.-ATE maker Credence Systems recently sold socket and test interface maker Dimensions Consulting Inc. (DCI), Santa Clara, and simultaneously announced the acquisition of Optonics Inc., Mountain View.

The DCI sale involves a management buyout, with Zaid Ayoub, a DCI founder, continuing as president. Financial terms were not disclosed, but Credence said it will take a writeoff of $5.1 million in Q4 of 2002.

Credence said the Optonics acquisition was an all-stock deal for two million Credence shares. Optonics is, according to Credence, "a supplier of integrated solutions for emission optical diagnostics and failure analysis."

DCI represents an earlier merger of Liberty Research and DCI. The company became a Credence subsidiary in January 2000.

Initially Credence acquired DCI with thoughts of making the company a captive test interface supplier. Credence's internal needs did not provide enough business "so we had to continue to look outside for customers," Nick Langston Sr., product line manager for sockets, told Chip Scale Review.

Focusing on Core Competencies

In a prepared statement, Carlos Lazalde, a Credence senior vice president, noted, "Given the current economic conditions, we will focus on our core competencies to produce the most cost-effective test solutions for our customers."

Lazalde added that Credence plans to continue using DCI "as a low-cost provider of custom technical solutions." [dci-us.com]

Bassam Asfoor

Yamaichi Electronics Names Asfoor Regional Sales Manager

San Jose-Yamaichi Electronics USA Inc. has appointed Bassam Asfoor regional sales manager - central region, reporting to Al Muranaga, senior vice president of sales and marketing. Asfoor will be based in Gilbert, Ariz.

A 19-year veteran of the test and burn-in market, he joined Yamaichi from CEIBIS Cody Electronics Inc. Earlier, he was a marketing manager at Agilent Technologies and sales director at Pycon Inc. He holds a BSEE from San Francisco State University and an MBA from the University of Phoenix. [yeusa.com]

 
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