By Prof. Rao R. Tummala, Packaging Research Center, Georgia Institute of Technology, Atlanta

In the System-on-Package (SOP) concept, the chip-size package is the system. While "systems" of the past consisted of bulky boxes housing hundreds of components performing one task, the SOP concept consists of mul-tiple system functions.

These functions include computing, communication, consumer and bio-medical-not one or the other, but all these functions in a small, package-size system, no greater than the size of Intel's Pentium processor package. Thus, SOP (System-on-Package) can be considered the "package as the system."

Figure 1. Illustration compares MCM, SIP, SOC and SOP

MCM, SIP and SOC Differences

Among the common questions about SOP technology is, "How does SOP differ from SOC, SIP and MCM?

The schematics shown in Figure 1 convey all four concepts. The SOC concept, for example, seeks to integrate numerous system functions on one silicon platform, namely the chip.

If this chip can be designed and fabricated cost-effectively with computing, communication and consumer functions such as processor, memory, graphics, antennas, filters, switches, optical waveguides and other components required to form the system, then all that is necessary to package such a system is to power and cool it.

Therefore, if this can be realized, SOC offers the promise for the most compact, low-weight system able to be mass-produced. This has been and continues to be the roadmap of IC companies.

Accordingly, the key question is whether SOC can lead to cost-effective, complete end-product systems such as tomorrow's leading-edge cell phones, laptops and workstations.

Fundamental Limits

Researchers around the world, while making great progress, are realizing that SOC in the long run presents fundamental limits to computing and integration requirements for wireless communications.

SOC challenges include long design times due to integration complexities, high wafer fabrication costs, test costs, mixed-signal processing complexity and IP issues. The high mixed-signal costs are due to both active, but disparate, devices such as bipolar and CMOS transistors, SiGe and InGaAs mixed semiconductors, and passives such as RF, optical components and MEMS-based RF oscillators that must be integrated into a single chip.

SIP (System-in-Package)

SIP (System-in-Package), defined as the vertical stacking of similar or dissimilar ICs, in contrast to the horizontal nature of SOC, overcomes some of the above silicon limitations.

However, if all of the ICs in the stack are limited to CMOS processing, the end product is limited by the above fundamental digital and integration wireless barriers of SOC. Still, there are clear benefits to SIP, including simpler design, design verification and process, minimal time-to-market and minimal IP issues.

Because of these benefits, about 30 IC and packaging companies are gearing up in a big way to produce SIP-based multichip modules.

Regrouping Good Bare Die

How are these SIPs different from MCMs? The MCM was invented at IBM in the 1970s for the sole purpose of regrouping good bare ICs directly onto a ceramic package, since chips could not be produced with an acceptable yield on the original silicon wafer.

These original MCMs are horizontal or two-dimensional modules. The new SIP-based MCMs, however, are vertical or three-dimensional MCMs. SIP seems to come in two flavors: as a 3D stacking of similar ICs, such as DRAMS, and stacking of dissimilar ICs such as processor, DRAM or flash memory, designed to approach the system's needs.

SOP Variation

SIP can be thought of as a variation of SOP. The SIP presented here strictly interconnects silicon chips, in the same manner as MCMs, and is therefore limited by CMOS. But what if the SIP package contributes to the system goals in ways that CMOS alone cannot, such as by embedded digital, RF and optical functions?

This contribution, then, is clearly an evolution toward SOP since it optimizes IC performance. Together with embedded RF and optical functions, it brings synergy to the system in terms of cost, performance and micro-miniaturization.

The SOP paradigm goes one step further in overcoming both the fundamental and integration shortcomings of SOC and SIP, which are limited by CMOS processing.

While silicon technology is great for transistor density improvements from year to year, it is not an optimal platform for the integration of RF and optical components.

Figure 2. Intelligent Network Communicator circuit board

Moving to the Nanoscale

The SOP concept overcomes the fundamental limits of SOC. As IC integration moves to the nanoscale and wiring resistance increases, global wiring delay times become too high for computing applications.

This delay leads to latency, which can be avoided by moving global wiring from the nanoscale on ICs to the microscale on the package.

The wireless integration limits of SOC are also handled well by SOP. The RF components, such as capacitors, filters, antennas, switches and high-frequency and high-Q inductors, are best fabricated on the package rather than on silicon.

Figure 3. Substrate fabrication at the Georgia Tech PRC

Decoupling Capacitance

To meet the need for the amount of decoupling capacitance necessary to suppress the expected power plane noise (associated with very high-performance ICs that use more than 200W/chip), a major portion of the chip area would have to be dedicated to decoupling capacitance alone.

Semiconductor companies are not in the capacitor business; they are in the transistor business, and the highest Q-factors reported on silicon are about 10-25, in contrast to 250-500 achieved on the package.

Optoelectronics, which finds use today primarily in the back plane and is used for high-speed board interconnects, is moving onto the package as chip-to-chip, high-speed interconnections replacing copper and thus addressing both the resistance and cross-talk issues of electronic ICs. (Optoelectronics is likely to move onto the chip itself.)

Figure 4. An experimental wafer at the PRC

SOP Research

Since SOP is about component integration by embedding actives and passives, the research is pervasive. Integration of capacitors, inductors and resistors is ongoing at more than 20 labs around the world.

Figure 2 shows the first single-module SOP prototype, the Intelligent Network Communicator (INC), that includes integrated digital, RF and optical functions in a single module.

Research in embedded back plane optoelectronics is also underway. Georgia Tech's Packaging Research Center, (Figure 3) goes one step farther to design mixed-signal systems, fabricating ultra-high-density microvia wiring with 100 to 20 micron pitch. The PRC also integrates not just capacitors and resistors, but also filters, antennas and switches, as well as chip-to-chip optoelectronics with embedded waveguides, detectors, gratings and couplers.

The PRC's SOP research focus is by means of nine leading-edge testbeds in digital, RF, optical, assembly, thermal, mixed-signal test and reliability. The SOP concept, we believe, will be applied by package and board companies as well as by semiconductor companies, the latter as wafer-level SOP (Figure 4).

Prof. Tummala is a Distinguished and Endowed Chair Professor in electrical and computer engineering and materials science and engineering at Georgia Tech. He is also the founding director of the National Science Foundation's Engineering Research Center in System-on-Package technology. Additionally, Dr. Tummala is an Eminent Scholar for the State of Georgia. Before joining Georgia Tech, Prof. Tummala was an IBM Fellow, where he invented a number of major technologies for IBM products. He is a fellow of the IEEE, IMAPS, the American Ceramic Society and president of the IEEE-CPMT Society. [rao.tummala@ee.gatech.edu]