January - February 1999
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Adapting Waffle Packs to the JEDEC Tray Format
By Vern Solberg
Contributing Editor
In my September 1997 Application Notes, I challenged the industry to come up with some solutions for what many chip-size and fine-pitch BGA package manufacturers consider a dilemma: The need for a low-cost method of handling and shipping finished devices.
Fine-pitch BGA (FPBGA) and CSP device development has been on the proverbial "fast track," with more than 200 packages reported in development or in production by JEDEC members and almost 300 different configurations defined in EIAJ member surveys.
A small percentage of the packages may have a common outline typical of those specified in JEDEC MO-195, but contact pitch and ball sizes will often vary, and those comapnies developing a real chip-size package do not conform to a uniform profile or outline.
One of the leading tray manufacturers, Fluoroware Inc., has noted that the continued growth of CSPs has indeed created the need for a reliable and cost-effective solution. Trays are an absolute necessity for the handling and transport of components throughout back-end assembly, marking, inspection and test operations.
Dedicated Tooling
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| Fluoroware's universal JEDEC tray concept |
Fluoroware's unique tray-in-tray solution, for example, offers a practical and cost-effective alternative (see photo). The tray is designed to hold three of the company's waf§e-pack trays, which are placed inside a JEDEC-compliant (or universal) tray, allowing for interfacing with standard assembly and test equipment.
This approach offers users greater manufacturing §exibility, for they may choose from among approximately 1,000 of the companys existing 4-inch waf§e packs with different pocket sizes and features.
Because manufacturers can customize a tray with existing waf§e-pack inserts, they are able to provide a solution more quickly and less expensively than suppliers that must retool their JEDEC trays to accommodate each unique CSP. If a specific waf§e-pack tray is not immediately available, retooling a new design can be accomplished at a fraction of both the cost and lead time required for a new JEDEC tray.
Cost of ownership is further reduced since universal JEDEC trays are reusable. The tray-in-tray solution opens a new market for Fluoroware and others. The four-inch-square "waf§e- packs" were originally developed for use in bare-die transport or die-bond assembly processes. Since the tray-in-tray combines the features of a waf§e- pack and JEDEC tray, it can be used throughout the assembly and test of the completed FPBGA and CSP.
JEDEC-Compliant Tray
The Fluoroware JEDEC-compliant tray is molded of high-temperature Poly-ethersulfone (PES) static-dissipative plastic. Typical of several versions being offered by competing companies, the universal tray holds three 4-inch waffle pack trays.Waf§e packs are easily loaded into and out of the JEDEC tray. Once in place, they are designed to securely retain the waffle pack until released by the user. Additionally, the waffle packs are available in both bakeable and nonbakeable materials and in a choice of colors to help ease the identification of different components being processed within the same work environment.
Some trays have even been designed to "flip over," allowing the ball contacts to be exposed for inspection and to accommodate electrical testing (while in the tray carrier). Companies have developed dedicated JEDEC trays for the really high volume CSP applications typical of flash, DRAM, SDRAM and Rambus memory packaging.
CSP Standards
JEDEC JC-11 members acknowledged that the trend in IC packaging is moving rapidly toward adapting the fine-pitch BGA format. The first chip-scale package outline to be registered in JEDEC was the Tessera-sponsored Thin, Fine-pitch BGA (TFP-BGA). This device outline moved through several ballot stages and was approved for publication in 1997. The 0.5-mm pitch array device described in the JEDEC MO-195 has a maximum height limit of 1.2 mm, defines a nominal contact diameter of 0.3 mm and allows for optional depopulation of contacts within the array matrix. Contact depopulation may include a zone within the array pattern or a selective deletion of contacts to enable efficient conductor routing on the circuit structure.JEDEC documents generally identify only the basic device structure, plastic, ceramic or tape, however; the MO-195 registered outline does not define the materials or method for manufacturing the device. And although the original TFP-BGA package outline data defines only the physical limits for a uniform square, flange-type chip-scale device, the document now includes several rectangular package variations.
The growing interest in this area prompted the establishment of a special working group for the task of developing the design parameters for future chip-scale and chip-size package outlines. The result of this effort is a new document that defines the requirements for a square FBGA package family having several optional contact pitch variations and establishing additional device profile variations. The JEDEC document for the FBGA package outline family, JEP95-1 Section 5, was approved in July 1998.
The infrastructure for chip-scale BGA package assembly continues to expand, and manufacturers developing equipment and materials will find a lucrative and growing market. In addition to those companies and systems described here, there are an increasing number of products available or in development throughout the industry.
International Standards for CSP
JEDEC and EIAJ are classified as country-based standards organizations, and even though JEDEC allows member companies from several countries to participate in the development of standards, the documents from either organization are not recognized internationally. For documents to be-come an international standard, member countries (not companies) must submit their document to the IEC (International Electrotechnical Com-mission). Countries will assign experts as delegates to represent their interest in selected IEC standards activity. Within the IEC there are several standards activities, ranging from components to manufacturing processes and materials, each assigned to specific technical commissions (TC). Component standards are in the jurisdiction of several IEC subcommittees, and IC device standards are assigned to a subcommittee identified as SC47D.
| Carrier/Container Sources for Fine-Pitch and Chip-Size BGA Packages | ||
|---|---|---|
| Company | Contact | Phone |
| 3M Company | Jill Nakamura | 408.354.0836 |
| Fluoroware | Ralph J. Henderer | 612.368.8626 |
| Gel-Pak | Jeanne Beacham | 408.733.1313 |
| Integrated Plastics | Richard Kraemer | 408.573.7071 |
| ITW Camtex | Ted Pappas | 510.490.5888 |
Because of the joint meeting activity between JEDEC and EIAJ, the information supplied by USA and Japan national committees are almost identical but some differences still prevail. For example, the USA National Committee proposal defines 0.50-, 0.65- and 0.80-mm as the optional contact pitch variations, while the Japan National Committee proposes the addition of 0.40 mm pitch to the package family. Both JEDEC and EIAJ documents describe a flange-type package structure with 18 size variations—the smallest outline is 4.0 mm square and the largest is 21 mm square—and a wide range of package height options.
Periodically, this magazine will provide supplier information and general features of equipment as specifications and data are made available. Thanks to Ralph Henderer, Fluoroware Inc., for information furnished for this column.
We would like to hear from you. If you have any comments or ideas you would like to share with other users of chipscale packaging technologies, contact Vern Solberg, Contributing Editor for Applications and Standards, at 408.383.3614 or vern@tessera.com