January - February 1999
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Welcome to the Year of the Chip-Scale DRAM
By now, both Chinese and non-Chinese in the electronics industry probably feel that the Tiger's reign during 1998 was an unduly long and harsh one.
On February 16, which marks the second new moon after the winter solstice, Chinese throughout the world will celebrate the beginning of "The Year of the Hare."
While hares are not rabbits, they hail from the same "Leporidae" family (according to Grolier's Encyclopedia), and are very swift animals. As such, they are likely to prove an appropriate metaphor for chip-scale-packaged memory in the year ahead. Consider that no packaging/interconnect technology in the relatively brief history of electronics has ever moved forward so quickly.
This year, as we move relentlessly toward the millenium--directly into "The Year of the Dragon," we expect to celebrate the volume acceptance of the CSP as a principal package for §ash memory and DRAMs.
Although we witnessed a retrenchment by some semiconductor equipment makers and suppliers during the last quarter of 1998, there has been no letup in the continuous effort companies are making to move the technology forward as a leading packaging medium.
Why? The acceptance of the CSP for memory by AMD, Intel, Texas Instruments and others, last year, positioned the technology for a major thrust this year. Additionally, bolstered by Hyundai's ChipPAC subsidiary, the CSP price point is rapidly falling to 0.5-1 cent per lead-achieving parity with the older, space-consuming--and less reliable TSOP.
As memory speeds increase and pincounts grow, memory suppliers are increasingly moving toward CSPs. For example, the Rambus Direct RAM requires a chip-scale package to achieve a 1.6 GHz data rate. And memory with a double date rate, offered by several vendors, requires CSPs for pincounts up to 90 pins.
It's time to look for volume production of memory in CSPs, even in Asia, where the economy was hardest hit. Furthermore, according to industry buzz, CSPs are achieving acceptance quickly enough to interest the makers of DSPs, logic devices and ASICs.
Several industry pundits are predicting that the worst is over. Take off your parkas and wading boots, and save them for some Alaskan ice fishing. Next, throw away your linament and crying towels. We predict that the sun will shine again, soon--led by chip-scale technology.
Clearly, wafer-level packaging has moved impressively to the front. It offers many advantages, including cost, throughput and yield, over conventional assembly line work. Anyone who is not developing a wafer-level approach is in danger of missing the market badly.
Throughout the year, we will continue to probe the yin and yang of the chip-scale market and to devise whether the predictions for memory are coming true. Our mission will be to keep you well informed.
As always, we look forward to your papers, comments and e-mail. Contact me at chipreview@aol.com. The Chip Scale Review staff will be at booth AR 110 during NEPCON West in Anaheim. Please stop by and give us your take on the year ahead.
Cordially,
