January - February 1999
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Opportunities and Challenges for Package Substrate Suppliers
To achieve the ideal of 0.5 cent/lead target, CSP substrate production must leverage the technology and volume production of BGA substrates.
By Dr. Dan P. Tracy, Rose Associates, Los Altos, Calif.
Strong growth opportunities and challenges exist for substrate suppliers vying for a share of the growing chip-scale package (CSP) market. The format's small form factor and excellent electrical performance are driving the CSP's growth.
Forecasts for overall CSP unit volume shipments forecast that an estimated 759 million units were shipped in 1998, increasing to over 3 billion units by the year 2002.1
One of the growing markets is for memory products, where several manufacturers of flash memory have announced production in fine-pitch ball grid array (FBGA) and Tessera's µBGA® packages.
An estimated 200 million flash memory devices were produced in 1997 and are forecast to grow to about 600 million units by the year 2000.2
In addition to flash memory, CSP packages are prominently listed on roadmaps for DRAM, beginning with the 64-Mb generation. Also, many memory applications will be stacked CSP modules.
Though indisputably a growing market, CSPs present challenges in terms of pricing and reliability, both of which impact the substrate material supplier and cover the spectrum of flexible, rigid (polymer and ceramic) and leadframe-based technologies.
Memory devices are assembled in low-leadcount packages, such as shrink small outline packages (SSOP), thin small outline packages (TSOP) and thin quad flat packs (TQFP).
In recent years, shrinking die sizes for high-density DRAM has led to the introduction of lead-on-chip (LOC) leadframe technology. Hitachi Cable, the leader in developing this technology, produces about 100 million LOC leadframes per month.
The CSP form factor is a natural extension of the LOC technology, because of its small footprint and thinness. LG Semicon assembles DRAMs in the LOC-CSP using leadframes manufactured by Hitachi Cable.
Though a growing market, CSPs currently represent less than 25% of the total IC units assembled, most of which are placed in leadframe packages. Over 70 billion IC leadframes were produced in 1997, with approximately 41 billion being small outline SO-type leadframes. These leadframe products are forecast to grow in volume by 10-15% CAGR over the next several years and will compete for market share with CSPs.
Beyond the systems which require a small form factor, pricing is a key factors determining how much of the leadframe-based packaging could and will transition to CSP. The ideal volume cost target for CSPs is 0.5 cent per lead.
Current pricing is estimated to be 1 cent per lead for leadframe CSPs and 1.5 cents or more for laminate and flexible substrate CSPs. In comparison, pricing for TSOP and SSOP packages is approaching 0.5 cent per lead.
In the past year, leadframes underwent severe price erosion and will continue to do so as the 40 or more leadframe suppliers worldwide compete for market share and position. Declining prices for TSOP and SSOP packages create a moving price target for CSPs.
Substrate Production
To achieve the ideal 0.5 cent per lead target, CSP substrate production must leverage the technology and volume production of BGA substrates. This holds true for laminate and tape-based CSPs that share common material and process technologies with BGA.The laminate and tape substrate markets are quite dynamic, with over 40 companies worldwide producing or announcing production plans. Increasing supply and volume production will contribute to the downward pricing of substrates. For example, increased volume production has contributed to a 40% price reduction for two-layer BGA laminate substrates in the past year.
In the area of laminate substrates, several new materials have been introduced to the market. Mitsubishi Gas & Chemical's Bismaleimide-triazine (BT) resin laminates are the de facto standard material for BGAs and are used in laminate CSPs.
The new laminate materials are based on advanced epoxies and epoxy blends, and have been introduced by Hitachi Chemical, Nelco International, Sumitomo Bakelite and others to compete with the BT laminates. These new materials may spur further reductions in substrate pricing.
TAB Applications
For tape substrate suppliers, reel-to-reel processing has a long history in electronic packaging in tape automated bonding (TAB) applications. High-volume production of tape substrates for CSPs will contribute to a reduction in package price and will allow the substrate supplier to achieve thin, fine-pitch interconnects. Pricing for tape substrates is reported to be high at this time, as overall production volumes are low.Besides price, package requirements present challenges with respect to reliability and performance for the material supplier, the package assembler and the board assembler. A number of papers have been published recently in Chip Scale Review documenting the board-level performance of various CSP designs.
The variety of CSP designs has led to the introduction of new material technologies that are still being characterized for performance.
| Suppliers with Build-Up Dielectrics for Package Substrates | |||
|---|---|---|---|
| RCC | Laser Dielectric | Photo Dielectric | |
| AlliedSignal | x | ||
| Amoco | x | ||
| BF Goodrich | x | ||
| Ciba Specialty Chemical | x | x | |
| Dow | x | ||
| Du Pont | x | x | |
| Enthone-OMI | x | x | |
| Hitachi Chemical | x | x | |
| MacDermid | x | x | |
| Matsushita | x | ||
| Mitsubishi Gas Chemical | x | x | |
| Morton | x | ||
| Park (Nelco) | x | x | |
| Shipley | x | x | |
| Sumitomo Chemical | x | ||
| Taiyo Ink | x | ||
One reliability issue for all plastic packages is the moisture resistance during solder reflow. Delamination and package cracking have been items of concern with leadframe-based packages and have pushed development of advanced molding compounds and die attach materials.
These same material advancements are required for laminate and tape CSPs, although moisture absorption by the polymer substrate is an additional concern. At minimum, packages must pass JEDEC Level 3 or better moisture test conditions.
Moisture reliability also depends on the test conditions:Does the customer require 220°C or 235°C solder reflow conditions during testing? This question is being debated and addressed by the semiconductor industry.
The thinness of tape substrates presents additional challenges in terms of handling and substrate warpage. Package manufacturers attach the tape substrate to carriers to ease and standardize handling during assembly; however, attaching the film to the carrier is an additional process step at assembly.
Stiffeners are required to improve handling but should do so without sacrificing thickness. (Stiffeners offer the potential benefit of enhancing thermal performance of the substrate to provide power dissipation beyond 1W.)
Other problems with tape substrates requiring material engineering solutions are due to differences in CTE between the various materials. CTE difference between the polyimide film and solder mask induces warpage of the substrate, resulting in loss of ball coplanarity. Obviously, much room exists for understanding and improving material performance of substrate packages.
Flip-chip CSPs demand materials and processes for manufacturing substrates with fine-line features, compatible with flip-chip reflow conditions and package reliability requirements.
Substrate Manufacturing
Tape substrate manufacturing holds advantages over laminate substrates in achieving fine-line and via features. A supplier base for build-up dielectrics for laminate substrates is evolving out of the microvia material market. This materials market is currently playing catch-up for build-up substrates, where material thickness tolerances, metalization, and adhesion are critical areas that need to be addressed for flip-chip technologies.Besides the demanding material requirements for these substrates, new equipment and processes will be needed to meet design rule requirements.
The substrate market for CSPs is obviously a growing one for material suppliers, although challenges exist in terms of pricing and performance. To capture a greater share of the leadframe market, CSP technology prices will have to decline.
Meanwhile, standardization of reliability requirements will facilitate the development of materials and contribute to the desired price structure for chip-scale packages.
References
- E. Jan Vardamann, "CSP and BGA Package Trends and Forecast," Proc. of EMCON 1998.
- Electronic Buyer's News, CMP Media, August 11, 1997.
Dr. Tracy is a veteran observer of the semiconductor industry and an industry analyst at Rose Associates. Readers may contact him at dptracy@ix.netcom.com