January - February 1999
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Meeting the cost/performance requirements of Flex-Based Chip-Scale Packages
Today, flex is the leading substate for building a chip-scale package because of its high circuit-density-to-cost ratio.
By Dr. Randy D. Schueller, Elizabeth A. Bradley and Paul M. Harvey, 3M Electronic Products Division, Austin, Texas
According to techsearch international, there will be 861 million flex-circuit-based csps sold in the year 2000, which is nearly half of their overall csp forecast of 1,885 million units.
Introduction
A number of terms have been used to refer to small-form-factor packages, such as chip-scale, chip-size, near-chip- scale and fine pitch. However, the name is not as important as the user's concerns that the package is small enough for the application, that reliability and performance is sufficient and that the total applied cost is minimized.The term "chip-scale package" (CSP) will be used for this paper, although it is recognized that the packages discussed are not always less than 120% of the die size, since this depends on the size die that is placed in the package. The authors believe this widely-recognized term best describes the variety of small-form-factor packages that are becoming increasingly popular among designers of portable electronic devices, laptop computers, telecommunication systems and other areas where size is of critical importance.
Because of the demand for CSPs and the large number of creative individuals in the field, there is no shortage of package options. The over 50 available CSPs are often grouped in four categories according to their substrate:
- leadframe-based
- rigid-substrate-based (PC board or ceramic)
- wafer level
- flex-circuit-based
Attractive Characteristics
Flex circuits offer an attractive combination of characteristics suited for this market. A number of flex producers today can handle design rules of less than 65µm pitch, whereas circuit boards are closer to three times that value. Consequently, most of the fine-pitch BGA patterns (as low as 0.5 mm ball pitch) can be routed on a single metal layer.The via sizes on traditional PC boards (typically 0.5 mm or larger) can make routing these finer-ball-pitch packages all but impossible.3 Flex circuitry is also not new to the packaging industry. In the form of TAB tape, flex has proved that it can survive the harsh reliability conditions expected of an IC package.
PC boards, on the other hand, are relatively new as a first-level interconnect substrate, with BT resin being the first substrate to prove itself capable. Another important advantage of flex is that there are numerous producers in the market, providing for a more stable source of supply.
Users are sensitive to this fact, due to issues experienced with a sole source of supply for BT resin. Flex also provides a thinner package, which can be advantageous in a number of applications.
There are a large number of flex-based CSPs available. However, only a few of the more prominent ones will be mentioned in this paper, which will examine their advantages and appropriate market segments.
Wire Bond Flex BGA
Today, wire bond flex BGA (known by such proprietary names as µStarTM at Texas Instruments and fleXBGA™ at Amkor) is the highest volume form of flex-based CSP. This construction is illustrated in Figure 1.
Figure 1. Wire-bonded flex BGA in a near-CSP format (fan-in and fan-out)
The assembly of the package closely follows the standard PBGA packaging process, with the only modification being an added procedure for rigidizing the flex so that it handles like a strip. There are two main methods of achieving this goal: one is to align the tape to a metal fixture with tooling pins; the other is to laminate a metal frame using an adhesive.
Low-Cost Method
This appears to be the lowest-cost packaging method, since for most die sizes, the package can be routed with low-cost, single-metal-layer flex. For example, a ball array 4-6 rows deep can be routed at 0.8-mm pitch. Since this package can easily support either a fan-in or fan-out ball array (or a combination of both), a larger number of balls can be routed by slightly expanding the package body size. This versatility also enables the package to be designed to minimize expensive fine-pitch routing on the board. In addition, the die size can shrink for the same package and footprint.There has been some concern about board-level reliability of this type of package due to the close proximity of the die to the board, with only the die attach adhesive providing compliance for CTE mismatch. However, data generated by Amkor and Motorola (Figure 2), has shown that this package, with 0.8-mm ball pitch and die sizes of less than 10 mm, provides sufficient board-level reliability for many applications.5
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| Figure 2. Board-level thermal cycle reliability for a 12-mm, 144-I/O package with 9.5-mm die size (-40C -125°C, 1 cycle/hr): Results shown are for a 0.9-mm-thick test board(#20) and a 1.6-mm-thick test board (#19). |
- Extra handling required for flex
- Board-level reliability for 0.5-mm ball pitch and for larger die/package sizes
- Need for a solder-mask dam to prevent adhesive bleed onto wire bond fingers
The µBGA® Package
The Tessera µBGA package (Figure 3) is arguably the best-known of the flex-based CSPs. Modifications, such as gold-plated copper leads and silicone nubbins, have been made over the years to improve this package; however, the concept is basically unchanged. A compliant elastomer layer is used to isolate the CTE mismatch stress of the die from the motherboard, prolonging the solder-joint life.
Figure 3. Tessera's µBGA package with fan-in ball pattern: The elastomer layer is used to absorb the CTE mismatch strain.
The µBGA package has also proven itself to be quite moisture resistant and is qualified to JEDEC level 2.6 In its standard form, this is a true chip-size package; therefore it enables only a fan-in ball layout. This makes the Tessera package a good solution for applications with a high die size-to-ball count ratio (such as various memory die), but it is less attractive for applications where some degree of fan-out is desired.
Incompatibility with the existing infrastructure is the largest barrier to overcome with the µBGA package. However, much has been done to develop new process steps and specialized equipment for this package. A thermocompression bond is used to interconnect a lead on the tape to the die, so the versatility of a standard wire bond is not realized, but the electrical inductance is minimized. Today, there are more than 20 licensees for this package technology.
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| Figure 4. E-CSP strip of 7-mm (64 I/O) packages at 0.5-mm ball pitch in an array format. |
The E-CSP substrate from 3M is one of the newer constructions in the market. This patent-pending product is similar to the flex BGA but includes some significant enhancements. The E-CSP is constructed by laminating a patterned 5-mil copper leadframe to the flex circuit (The carrier strip is shown in Figure 4, and a drawing is shown in Figure 5).
Figure 5. Enhanced CSP structure is shown in a CSP format. Copper interposer enables a matched CTE to the board.
Typical die attach adhesives are used to adhere the IC to the surface of the leadframe. The IC is then wire-bonded to the circuit through slots or openings in the leadframe. Overmolding takes place, and the parts are singulated from the strip. (A cross-section is shown in Figure 6.) This package provides the following enhancements:
- Improved board-level reliability
- Improved heat dissipation
- Easier handling in assembly
- Improved coplanarity for larger packages
- Elimination of solder-mask dam
Figure 6. Cross-section of an assembled E-CSP (12 mm, 144 I/O)
Board-Level Reliability
For relatively small die sizes at 0.8-mm ball pitch, adequate board level reliability has been demonstrated for many applications with the wire-bond flex BGA package. However, as the die grows larger and/or the ball pitch is reduced, the lack of an adequate interposer will likely become a more important issue.The E-CSP uses the 5-mil copper as an interposer. Using a high-temper copper alloy with a CTE value which closely matches the board allows, the solder joint stress normally associated with the low CTE of the die to be shielded. A moirÚ fringe analysis was performed on the ball side of a fully assembled 12-mm E-CSP package with an 8.8-mm die to determine the effective package CTE in both the x and y directions (shown in Figure 7).
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| Figure 7. Illustration shows the moirß fringe pattern of an assembled 12-mm E-CSP. This method revealed a package CTE of 15.5 ppm/°C in the x-y direction. |
A 2,400 lines/mm grating was created on the ball side of the package and the CTE was measured between a temperature range of 22°C and 82°C. Three samples were measured in both the x and y directions. The resulting mean of 15.5 ppm/°C more closely matches the CTE of a circuit board (typically between 15 and 18 ppm/°C) than would a package without the interposer. A wire-bond flex BGA has an effective CTE of only 4.3 ppm/C and can create a high stress on the solder joints.0
In addition, an ANSYS two-dimensional, mechanical stress/strain model was created to compare a 12-mm flex BGA structure directly to the E-CSP in a board-level condition.
The model in Figure 8 predicted the Von Mises cumulative effective plastic strain in the solder ball after five cycles from -55/125°C. The strain is 88% in the flex BGA compared to only 17% in the E-CSP.
The material set selected for this package will determine the package-level reliability. Only a few materials have been evaluated thus far. When constructed with JMI2500B or Hysol KO120 die attach adhesive and Sumitomo 6600CR overmold compound, the package passed JEDEC A112 moisture level 3 and 168 hours of pressure cooker testing with no electrical failures. Additional materials are currently being evaluated.
To determine the heat dissipation capability of the E-CSP package structure, a number of thermal models have been created for packages and die of various sizes. The basic finding is that the copper interposer provides an increasing benefit over a wire-bond flex BGA package as the body size-to-die size ratio increases.
The copper interposer effectively spreads the heat from the die over all the balls in the package and provides an efficient thermal path to the mother board (Figure 9). The graph in Figure 10 shows comparative thermal results for a 16-mm die in a 27-mm package (676 I/O). The 27% difference in Theta Ja between these two structures would increase further as the die size was reduced, or if the heat-spreader thickness was increased. It is anticipated that the E-CSP structure could handle a die of over 5 watts with no airflow (depending on the specifics of the application, of course).
Infrastructure
Handling bare flex has been an important issue since its inception. However, laminating the flex to a rigid leadframe eliminates these issues. Throughout assembly, the resulting strip can be handled like a conventional printed circuit board.As with a board, the utilized area is a large component of cost with a flex circuit. Minimum cost is thereby achieved though optimization of component density in the strip. For smaller package sizes this often means the packages should be laid out in an array format in the strip and singulated with a dicing saw. The rigid strip format is also more conducive to efficiently performing testing of all packages while still in the strip prior to singulation.
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| Figure 8. Graphic shows ANSYS mechanical stress-strain model for E-CSP compared to wire bond flex BGA when thermal cycled from -55°C to 125°C. |
Flip-Chip CSP
Flip-chip interconnection has traditionally been used primarily in two markets. For direct attachment to a board for low-end applications, such as watches, or for attachment to a multilayer ceramic (or more recently PC board) package substrate for high-end mainframe applications.
Figure 9. E-CSP structure in a larger format for improved heat dissipation and higher I/O is shown. Slots for wire-bond pads are separated by metal tabs at the corners of the package.
The real volume opportunities, however, lie in the mainstream mid-range markets, such as cellular phones and personal computers. To penetrate these markets, packaging costs must be reduced to be competitive with existing wire-bonded packages, such as QFPs and BGAs (0.6-0.8 cent/lead). Direct chip attach (DCA) to a circuit board is not popular in these markets, due to the issues associated with underfill (this process does not fit typical board assembly shop capabilities and rework is very difficult).
A number of companies are examining the use of low-cost PC boards or flex circuit substrates as a flip-chip interposer. The chip can be attached and underfilled, the solder balls attached, the package electrically tested and singulated and then presented to the board assembler like any other BGA package.
Figure 10. Graph shows thermal modeling results for an E-CSP compared to a standard wire bond flex BGA (16-mm die in a 27-mm package are 4-layer board).
Flex works well as a flip-chip interposer due to its finer pitch capability. Two-metal-layer flex might be required if the interposer is to be used as a redistribution layer, depending on the ball pitch and I/O count (as shown in Figure 11).
There are a number of advantages to flip chip compared to wire bonding. For example, electrical performance is significantly improved. However,the real driver for mainstream markets is cost. The process of bumping a wafer, reflow attaching to a substrate and underfilling must be lower-cost than die attach, wire bonding and overmolding.
Flip chip has the added advantage of enabling more I/O per unit area on the chip, thereby enabling die shrink cost reductions for pad-limited die.
The graph in Figure 12 shows that for typical ball pitches of 250 µm, a die of over 200 I/O can be reduced beyond pad-limited size (assuming 70-µm effective wire bond pitch). If the flip-chip ball pitch is reduced further, then pad-limited die of even lower I/O count can be shrunk. This calculation does not take into account the size added to the chip to make room for the wire-bond pads. A flip-chip die has a further advantage, since bumps can be placed directly over active areas, saving real estate.
Figure 11. One example of a two-metal-layer, flip-chip CSP in which redistribution is performed on the package.
A recent paper by Mistry, et al., compares flip-chip attach to various thicknesses of circuit boards to thin flexible circuit attachment.8 Surprisingly, the thin flex actually performed significantly better in board-level, thermal cycle testing than did the thicker board substrates.
Thermal cycling from 0°C to 100°C resulted in a characteristic life of 5,524 cycles with a beta slope of 11.1. This is over 2 times better than a 1-mm thick PC board substrate.
Although much of the attention in the U.S. has been on solder-attached flip-chip, it appears that Japanese manufacturers and users are more focused on an anisotropic conductive adhesive as an interconnect method. Use of such an adhesive is attractive, since it eliminates the underfill process.
Figure 12. This graph displays effective wire-bond pitch vs. flip-chip ball pitch for various die I/O counts. Situations with an effective wire bond of less than about 70 µm enable die shrink.
Due to concerns over reliability, these adhesive materials are first being implemented on lower-end products, with the potential to migrate to more sophisticated applications if the reliability is proved. As more companies begin to seriously focus on implementing various forms of flip-chip attach, flex circuitry will likely begin to play an increasingly important role.
Applications for Flex-Based CSPs
Flex-based BGA packages offer a much needed small-form-factor package to a variety of markets. Memory is a logical area for flex-based packages, and the industry has seen successful implementation of both µBGA packages and wire-bond flex BGAs. However, because flex substrates offer a superior routing capability compared to rigid substrates, they are also ideal for logic devices with higher I/Os. Below is a discussion of the role of flex-based CSPs for logic devices in the telecommunications equipment, graphics chip and portable electronics markets.
Telecommunications Market
Chip-scale package designers have largely overlooked the telecommunications equipment market, because one does not typically associate large pieces of equipment with a need for a small-form-factor package. But this industry can gain large cost savings and increased product functionality by using near-chip-scale packages. CSPs allow designers to pack more chips and more functionality into a given board size. Therefore, designers can either increase the functionality of the product or decrease the number of boards and lower overall cost.The wire-bond flex BGA and the E-CSP discussed above are excellent candidates for this market. The combination of the cavity-up construction, which allows routing directly under the die, and the fine-pitch capability of flex, allows designers to route more I/O in a given area. This is important for telecommunications logic ICs, such as ASICs, PLDs and DSPs that may typically contain 200-500 I/O. In addition to high-density routing needs, two other factors play a role in determining what kind of flex-based BGA package is used in this market. These include heat dissipation and board-level reliability requirements.
A wire bond flex BGA should be adequate when devices are dissipating less than 2 watts. In many cases, the device is dissipating greater than 2 watts, so a heat sink must be added or an enhanced BGA is required.
As mentioned earlier, the copper interposer in the E-CSP can accommodate heat dissipation by spreading the heat from the die over the balls in the package to the printed circuit board. The exact heat dissipation capability of this package is dependent on many factors, including die size, package size, air-flow, proximity to other devices and the construction of the PC board. Thermal modeling of the E-CSP (Figure 10) provides a Theta Ja of less than 16 C/W for a 5-watt device.
Regarding board-level reliability, various factors, including die size and ball pitch, affect the performance of a package. For the higher-performance telecommunications market, die size causes the greatest concern, since die can be quite large (over 12 x 12 mm). The copper interposer in the E-CSP decouples the die from the solder balls, reducing the effect of the CTE mismatch between the die and the printed circuit board.
Graphics chips for desktop and portable computers have traditionally used cavity-up PBGAs. Heat dissipation is important to this market, since many devices require 2-10 watts of power dissipation. A PBGA typically requires a heat sink for these applications. The E-CSP package offers improved heat dissipation without a heat sink, since it can dissipate up to 50% more heat than a typical PBGA.
This allows the designer to exclude the heat sink for devices dissipating less than 6 watts. Eliminating the heat sink lowers the overall cost and reduces the space needed for the package.
In addition to decreasing the height of the package, E-CSP can also provide the same I/O capability in a smaller-outline package. For example, 256 I/O can be easily routed on one metal-layer flex in a 17-mm package, or up to 484 I/O in a 23-mm package with 1.0-mm ball pitch. This smaller package can result in a significant cost savings, especially if the E-CSP is used to replace a larger cavity-down enhanced BGA.
The use of CSPs in portable electronics has been increasing rapidly over the last few years. Wire-bond flex BGAs are
proving their capability by meeting board-level reliability requirements, decreasing the area required on the board and by providing a thinner package.
The E-CSP offers advantages that may be needed in the future by the portable electronics market. Where board-level reliability is concerned, ball pitch is more of an issue than die size, because die sizes are relatively small. As ball pitches migrate to 0.5 mm, adequate board-level reliability becomes questionable with a flex-only package, since the opportunity for solder ball cracking will increase with the smaller-diameter balls. In addition to the benefit of improved board-level reliability, the stiffener also acts as an inhibitor for die-attach bleed, eliminating the need for a solder mask or cover coat.
Flip-chip CSPs may also play a role in portable electronics, since form factor is one of the main drivers for this market. As mentioned, however, overall cost must be competitive with wire-bonded solutions. A simple, low-cost, one-metal-layer flex substrate should be adequate to route the I/O for many of these applications, but the infrastructure and assembly processes are still being developed.
Conclusions
Flex is the leading substrate for building a chip-scale package, due to its high circuit-density-to-cost-ratio. It is also helpful that there are many flex-circuit suppliers already in the market. Flex-based CSPs with different characteristics are rapidly being developed to satisfy the needs of several market segments.Tessera's µBGA package and the wire-bond flex BGA appear to be the leading candidates for the memory market today. The needs of the portable electronics market seem to be filled by the wire bond flex BGA today, and possibly by a flip-chip CSP in the future.
However, for higher-end applications, such as graphics and telecommunications, the E-CSP may be the best choice, due to its improved board-level reliability and ability to dissipate heat.
Applications which now use a peripherally routed, enhanced cavity-down package may turn to a fully populated E-CSP in the future to reduce package size and cost while maintaining both thermal and reliability requirements.
Acknowledgments
The authors gratefully acknowledge T. Hayden, B. Inks and B. Clatanoff for building samples and gathering reliability data on the E-CSP.References
- R. Iscoff, "Two Reports Predict Bright Future for CSPs," Chip Scale Review, May 1998, p. 22.
- BPA Group Ltd., "Technology Update No. 3," February 1998, p. 2.
- G. Gengel, "Survey of Film Based CSPs," Proc. of Chip Scale International, May 5, 1998, p. 89.
- Prismark Partners LLC, "Chip-Size Packages—We Have Lift Off," December 1997, p. 2.
- R. Darveaux, J. Heckman and A. Mawer, "Effects of Test Board Design on the 2nd Level Reliability of a Fine Pitch BGA Package," Proc. of Surface Mount Int'l., August 1998, p. 105.
- R. Bauer, "Advanced Chip-Scale Packages Offer Manufacturing Advantages," Proc. of SMTA Nat'l Symp. Bloomington, Minn., October 1997, p. 167.
- R. Schueller, "A New, Enhanced Flex-Based CSP with Improved Board Level Reliability," Proc. of SMTA Nat'l Symp, October 1997, p. 187.
- A. Mistry, et al., "Reliability of Low Cost, Fine Pitch, Flip-Chip PBGA on Flex and Rigid Substrates," Proc. of Chip Scale International, May 6, 1998, v. 2, p. 121.
- T.I. Ejim, "High Reliability Telecommunications Equipment: A Tall Order for CSPs," Chip Scale Review, November-December, 1998, p. 44.
Authors
Dr. Randy D. Schueller is a senior product development specialist and a development team leader for 3M's Microflex Advanced IC Packaging Group, Austin. He has authored 16 papers and has four issued patents in IC packaging. Dr. Schueller received his bachelor's degree in physics from St. John's University and his master's and PhD in materials science and engineering from the University of Virginia. Contact him at rdschueller@mmm.com or by phone at 512.984.5145.
Elizabeth Bradley is market development supervisor for the Electronic Products Division of 3M. She earned an MBA from the University of Texas at Austin and a BS degree in mechanical engineering from Texas A&M University. Contact her at ebradley@ mmm.comor by phone at 512.984.6699.
Paul Harvey is a senior product development specialist in the Electronic Products Division Lab at 3M in Austin. He holds a BSChE from Brigham Young University and an MSEE from Syracuse University. Contact him at pmharvey1@ mmm.com or by phone at 512.984.5784.