January - February 1999
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It's Flexibility vs. Simplicity in Standardizing Chip-Scale Packages
By James Hayward, Contibuting Editor
Aside from the decreased board area that a chip-scale package occupies, one of the benefits of using a CSP is the reduction in overall height of the package with respect to a more conventional one. CSPs predominantly fall into the categories of low-profile, thin-profile or very-thin profile as established by JEDEC and EIAJ.
These categories define overall height as L-<1.7 mm, T -<1.2 mm and V -<1.0 mm. These are the overall package heights which are required by most of the small portable products being manufactured today or being introduced in the very near future.
The T and V limits, in particular, have been difficult for standard packages, such as QFPs, to meet. The ability of chip-scale packages to combine reductions in board area and height together is a major reason for their rapid acceptance by users.
The overall height for a specific package type is the A dimension defined in the standard or registered outlines in JEP-95 for JEDEC and in the ED-xxxx documents for EIAJ.
Many Factors
The value of A is a result of many factors including the choice of materials, die thickness, reliability requirements, etc. For leadframe-based packages, such as the SON where the package body is defined largely by the molded encapsulant, the overall height is essentially defined by die thickness and molding capability, as shown in the accompanying illustration.Many of these packages have the potential to be much less than 1.0 mm in height. For the BGA-type CSPs (FBGAs), overall height results from a combination of die thickness, wire-loop requirements, encapsulant thickness (if any), substrate type and thickness and solder ball geometry. The more complex set of factors in the FBGA case impact standards for ball geometry in particular.
Since the ball geometry is a function of the array pitch and affects the package height, both factors must be considered when designing or standardizing FBGAs. In addition to the body thickness, the overall package height, dimension A, includes the ństandoffî height, dimension A1.
In general, A1 is defined only as a minimum value based on the minimum ball diameter, dimension b, allowed for the FBGA: A1(min) = 0.60 x b(min). This relationship recognizes the transformation of the spherical raw solder ball into a truncated oblate spheroid when it is attached to the FBGA substrate.
(Although most drawings represent solder balls as truncated spheres on the package, they are usually larger in diameter than the original raw solder ball due to collapse on the solder pad.) The result is that the minimum A1 value is smaller for smaller ball diameters. Again, generally speaking, the reliability under specified stress conditions of the solder joint resulting when an FBGA is attached to a board is greater when the standoff height is larger.
Starting Point
Thus, for a given package type, the designer (and end user) would like to use the largest ball diameter possible. As a starting point in both JEDEC and EIAJ, the nominal values for dimension b, the solder ball diameter, are defined as a function of the array pitch, dimension e (BSC): b(nom) = 0.60 x e (rounded to the nearest 0.05 mm increment). Thus, for 0.80 mm pitch, the primary value for b(nom) is 0.50 mm; for 0.65 mm pitch, it is 0.40 mm, and for 0.50 mm pitch, it is 0.30 mm. The nominal values have ± 0.05 mm tolerances.The difficulty in applying these basic rules for ball diameters for the package designer comes from the variety of materials and construction used for the FBGA. Substrates may range from
50-µm thick polyimide tape to 250-µm thick BT or other laminate material.
For the very thin (V) profile packages, only the thinnest materials may be feasible, but for packages in the L or T categories, thicker substrate materials can be useful and desirable. The thicker substrate materials may, however, force some reduction in other height components in order to maintain compliance with the profile requirement.
Thus, die may need to be thinner, wirebond loop height may need to be smaller or overmold thickness may have to be reduced. Another option is to employ a smaller ball diameter where the array pitch allows and thus reducing A1. Decreasing the ball diameter is clearly limited by the array pitch and for many FBGA pitches there is little option for such a move.
For 0.80 mm pitch, however, both the 0.40 mm and 0.30 mm ball diameters are feasible, and for 0.65 mm pitch the 0.30 mm ball pitch is feasible. In the JEDEC FBGA Design Requirements document now pending approval at the JEDEC Council, the allowable ball diameters are defined in just this way. For 0.80 mm pitch, ball diameters of 0.50 mm, 0.40 mm and 0.30 mm are allowed; for 0.65 mm pitch, ball diameters of 0.40 mm and 0.30 mm are allowed; for 0.50 mm pitch, only the 0.30 mm ball diameter is allowed.
Overall package height is essentially defined by die thickness and molding capability, as shown.
However, any specific package variations defined in an outline registration or standard can have only one of the allowed ball diameters. In most cases a single ball diameter is defined for an entire document as a common dimension for all variations such as in MO-195 and MO-205. In other cases, such as MO-207, the ball diameter is specified on a variation by variation basis.
In either of the above cases, the user will be able to determine the ball diameter for a package by reference to the specific JEDEC outline variation. The difficulty for the user is that similar package outlines, which differ fundamentally only in ball diameter, may require board layout modifications.
Different solder ball diameters will likely require different solder pad geometries on the board just as they do on the FBGA substrate. This issue has been the subject of lengthy discussion between the respective packaging bodies of JEDEC and EIAJ at joint meetings over the last several years.
JEDEC has argued on the basis of flexibility and EIAJ has argued on the basis of simplicity. It is likely that only the experience gained from expanding usage of these packages will allow complete resolution of the difficulty.
Mr. Hayward is a senior member of technical staff in the Manufacturing Services Group at Advanced Micro Devices (AMD), Sunnyvale, Calif. He has been the AMD member of the JEDEC JC-11 Committee since 1982 and was instrumental in developing the JEDEC outlines for BGA, PGA and TAB packages. Mr. Hayward can be reached at james.hayward@amd.com or by phone at 408.982.6427.