The adoption rate of new IC packages has been-and will continue to be-governed by several factors: the cost of the packages, available infrastructure, the compatibility with existing technology and the ability of PC board assemblers to reliably route and place the packages to the board. The semiconductor industry's ability to design and assemble very small, fine-pitch packages exceeds the practical limits of placing the devices reliably and cost-effectively on most production boards. Routing and placing these very small packages cost-effectively on a board has been the focal point of many discussions and has inhibited package designers from decreasing the pitch to the smallest proportions possible. The ability or willingness to handle these very fine pitches varies by region. For example, while many Japanese assemblers could work with leaded packages with I/O pitch as low as 0.3 mm, most U.S. PC board assemblers were never comfortable with leaded-package pitch below 0.5 mm. As a result, leaded packages with a pitch less than 0.5 mm are fairly rare in the United States.
A Less Demanding I/O Pitch Although array packages were originally created to meet the needs of high I/O-count devices, they have also provided the benefit of a less demanding I/O pitch-typically 1.27 mm for "full-sized" BGAs and 0.8 mm for CSPs. However, this pitch will drop to accommodate the continuing quest for smaller package footprints. For array packages, multiplying I/O pitch by I/O count essentially determines package footprint. Since I/O count is determined by device function, lowering I/O pitch remains the only way to reduce the footprint of most array packages. When the I/O pitch is lowered to where that die size begins to control the package footprint, the package has become a CSP. By our definition, CSPs begin at no more than 1.0-mm pitch and end at die size. However, except for devices with very large die and modest I/O count (e.g. DRAMs), the crossover between BGAs and CSPs does not take place until 0.8-mm pitch or below. The table presents our I/O pitch forecast for BGAs and CSPs. BGAs are generally at 1.27-mm or 1.0-mm pitch, although there are some below that figure. The trend is for a smaller pitch in the future, for an increased amount of BGAs at 0.8-mm pitch. CSPs are generally at 0.8-mm pitch, with 0.5-mm in most product roadmaps. Significant Increase
There will be a significant increase in the number of 0.5-mm pitch CSPs by 2003, but this will not be led by DRAMs. The typical DRAM die is large in relation to its I/O count and does not need 0.5-mm pitch. The move to the smaller pitch will be led by a variety of small-die devices used in handheld products.
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