An Independent Journal Dedicated to the Advancement of Chip - Scale Electronics March - April 2000 Email the editor

By Shaw Wei Lee, Dale Anderson, Luu Nguyen, and Hem Takiar
Package Technology Group, National Semiconductor Corp., Santa Clara, Calif.

The chip-scale package (CSP) has been widely used by the wireless and portable industries. With the increased demand for CSPs in high volumes, and the many CSP variations, National Semiconductor, whose wireless products generally run from 900 MHz to 2.8 GHz, has implemented a new manufacturing strategy, which employs integrated assembly and strip test.

The preferred package for supporting wireless products has migrated from the conventional TQFP and the TSSOP to the fine-pitch ball grid array and the CSP.

Assembly for the TQFP and TSSOP is typically accomplished with a matrix frame, while testing for TQFP and TSSOP formats is carried out in a singulated format. The TQFP and TSSOP can also be strip tested by trimming the lead tip from the tie-bar before test.

This paper describes the migration of CSP equipment from the conventional method to a fully integrated assembly and strip test manufacturing method.

Introduction

In the conventional substrate manufacturing process, the busline usually connects all the pads for plating, and the FBGA and CSP (Figure 1), have to be sawn into individual units for testing.

The major advantages offered by our new method are: A universal platform for assembly and test regardless of package I/O counts. Mapping/sorting is enabled for yield tracking during assembly and test. Higher throughput is achieved for assembly and test. The CSP, in general, is a smaller package compared to the conventional package format. Most CSPs are so small, that after assembly and singulation, handling becomes extremely difficult. A slight bump or jerk in handling will result in the packages being spilled all over the floor. When that happens, recovering the package is nearly impossible. Conventional assembly and test involves the major process steps shown in Table 1.

Figure 1. NSC's CSPs and FBGAs

Key Challenges

Front-end assembly and the backend test infrastructure have changed much in the past two decades. Although the equipment for assembly and test has improved significantly every year, the assembly and test process has remained constant.

As independent test consultant Jack Kessler has pointed out, change is certainly overdue, and a new paradigm shift in assembly and test must be considered.

The key challenges to be overcome are:

  •  Isolate the substrate pad from the adjacent pads

  •  Keep the warpage for the molded panel within the strip to a minimum.

  •  Ensure that solder pad size and location are accurate for contact consistency.

  •  Select the best strip test handler for the job.

  •  Select the appropriate sockets (contactors).

  •  Avoid ESD damage during sawing.

  •  Strip 2D cell, sort and mapping.

  •  Determine the trade-offs between singulated and strip-tested parts.

  •  Most important of all, guarantee 100% that no other additional damage is induced post-test.

Chemically Etched-Back Process

Most substrate suppliers can provide CSP/FBGA substrates using conventional manufacturing processes, in which the pads are all connected to the busline for Ni and Au plating.

The busline connecting the pads has to be removed to isolate pads for strip test. Other-wise, all the pads will be shorted together and strip testing will be impossible using the electrolytic plated substrate.

Certainly, other substrate manufacturing processes, such as gold etching or electroless plating could achieve the same isolation for strip test. However, package reliability and manufacturing consistencies may be compromised when using gold etching and electroless plating. The gold-etched substrate uses gold plating as the etching resist.

In this case, the problem is that adhesion between solder mask and the gold plating has proven to be very poor. The gold plating surface does not adhere well to any material.

The implication? The mold gate used for BGA and CSP substrates is gold plated for ease of degating after molding. The plating thickness control and consistency for the electroless process is not as good as with electrolytic plating. As a result, another problem associated with electroless plating is the poor wire bond yield.

Figure 2. Chemical etch-back and dual image substrate The alternative substrate solution for strip test is achieved by using a debussed or chemically etched-back substrate (Figure 2, top). In this substrate, the busline is removed after electrolytic plating. This is a process that has been employed by a few substrate manufacturers, and is much more reliable than the gold etch or electroless process for CSP strip testing.

For the dual row CSP, the dual image process (Figure 2, bottom) is used to achieve the same results as the chemical etch-back process. The dual image process is selected for the dual row CSP because routing the busline for the second row is not feasible for fine pitch (0.5 mm) solder pads.

Another major design consideration is the substrate metal balancing between top and bottom metals for a two-layer metal substrate design.

The balanced metal substrate design will minimize substrate warpage during assembly, where the warpage of molded substrates is primarily introduced by the choice of molding compound.

There are many versions of molding compounds offered to reduce warpage during molding. The warpage of the molded substrate strip will create problems at strip test as well as during sawing. Generally, higher glass transition temperature (Tg) (and lower viscosity) are desirable characteristics of mold compounds used for panel molding of CSP substrates.

A larger substrate area will likely result in more warpage of the panel. However, with the proper design of experiment (DOE), one could select a molding compound to achieve the desirable results. Large molded areas obtained with full strip flood molding (e.g., 200 mm x 50 mm) or panel molding exceeding 50 mm2 have been demonstrated by a number of companies.

Equipment constraints are the most important items to consider at this stage. While there are many ways to achieve high volume manufacturability for strip testing of CSPs, taking too much risk may result in a major failure. Alternatively, using a more conservative approach could be as bad or worse.

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