Solder Pad Design There are many CSP types available. Some feature solder balls while others may be designed with the land grid array form factor. In general, larger solder balls (or solder pads), facilitate the contact needed during testing. The higher stand-off obtained with larger solder balls will also produce better solder joint reliability. The only problem is that in the CSP arena, pad size area is very precious. With continuous shrinking of the CSP body size and pad pitch, the solder pad size is also being reduced. This has created a major problem for contact continuity during test. As a result, while contactor selection is important, pad design is even more important. National Semiconductor has introduced many versions of the land grid array CSP for high volume production. Two types of solder pad design are typically employed in the BGA and CSP construction. The solder mask-defined (SMD) pad uses the solder mask opening to define pad size. The SMD pad has created a problem for strip testing due to frequent solder mask registration error during substrate manufacturing. Solder mask shifting for BGA and CSP substrates can sometimes be as much as 50 microns. For a small pad size, a 50 micron shift may be quite significant, resulting in contact problems during testing. The contactor can touch down on the solder mask resulting in continuity failure. Poor solder mask etching or cleaning during manufacturing may also result in contact error. The other solder pad design is a non-solder mask-defined (NSMD) pad, in which the pad size is defined by the actual metal size. The solder mask is typically pulled back from the solder pads in this design. The NSMD pad is a better choice for CSP strip testing. Several test handler manufacturers are currently working on strip test handling solutions. MCT (Figure 3) and Delta Design are actively promoting an integrated handler approach. MCT seems to be further along the power curve at the time of this writing.
Tesec offers a handler with a slightly different design that employs a wafer ring on which the strip can be tested after singulation. Parts are removed from the wafer ring after test. Some of the key challenges for the strip test handler for CSPs are: • Alignment technologies • Strip identification • Strip mapping • Temperature conditioning • Retest capabilities • Debussing of strips • Index time • Parallel test and throughput Alignment technologies These have been used in similar steps of the semiconductor industry today, such as wafer probing. Adapting such technologies to strip test, while new to some test companies attempting the task, does not imply re-inventing the wheel or any major re-design or retooling. Strip identification This can be achieved by several methods, including bar codes 3 of 9, and 2D cell codes ECC 200, among others. The trick will be to find the one that best suits the operation and internal processes. It must take up as little valuable space as possible, and yet be further useable in downstream processes. Strip mapping This and the electronic transfer of maps is probably one of the key technologies that makes strip testing work. A process which is comparable or similar to wafer mapping and electronic transfer of maps to assembly sites can be done with strip map transfers from tool, to server, to tool. Map transfer can be accomplished throughout the assembly, test, mark, saw and tape and reel processes. Temperature conditioning Conditioning of strips will require new ideas in temperature control. The old method of creating a temperature chamber will no longer work because of XYZ-stage issues. Therefore, more localized conditioning methods must be developed. Various heat exchanging schemes that are employed by much of the available semiconductor equipment will work. Retest capabilities These can be accomplished by several methods, such as real time yield monitoring and retest with pre-programmed yield hurdles. Debussing Strip debussing is probably the single most important factor to enable strip testing. While most people in the semiconductor industry understand the need for debussing, it may still be overlooked or become an afterthought that makes implementation difficult, if not impossible. Debussing is needed for laminate-based CSPs, leadframe-based CSPs, as well as any type of matrix leadframe configuration. Index time Index time is one of the key enhancements to testing in strip/matrix format. Minimizing X-, Y- and Z-motion during test will reduce the indexing time to the bare minimum. Commercial wafer probers have done this for years. Hopefully, design and experience from the probe manufacturers' counterparts will migrate to test handler suppliers. Parallel test Parallel test methods for analog, mixed signal, and digital products will no longer be limited to the handler domain, but will only be tester-resource limited. With technologies learned from the memory manufacturers and new test players, testing of any number of parts will be possible. UPH throughputs in the five figures, thus far appearing only on the wish list of many users, will become a reality. Contactor Selection Contacting at strip test can be one of the more challenging areas for equipment and test engineers. The handler must be able to use a variety of contactor technologies. Several contactor companies are currently working on solutions for multi-site contactors for strip testing. In this case, contactor considerations are the same as with the singulated application, except for alignment characteristics. Alignment features must be embedded in a design that will allow the handler's vision technology to find the contactor in space. Further considerations for test development must allow for manual verification of singulated parts outside of the handler environment. Contactor designs also need to be customized for the strip design. These designs should take into account contactability and optimum multi-site test performance. Figure 4 shows two contactor designs that take advantage of the strip's design for testability.
New tapeless saw machines have been developed by a few suppliers. Tapeless saws are an ideal way to eliminate ESD changes for the saw operation after strip test. The only concern about tapeless saws currently is their newness to the industry. They need to be proven through extensive handling in high-volume production environments. Strip 2D Cell, Sort and Mapping The laminate substrate can be designed with a dedicated area for a 2D cell for strip identification. This 2D cell can be readily incorporated for strip identification using a laser for strip test and mark integration block. The preferred approach is to obtain substrates already marked with a strip ID, and work with the substrate supplier to create an inkless map of all the reject CSP sites. Although the equipment infrastructure exists, most substrate suppliers do not have the laser marking equipment or the read/write capability to implement this 2D cell, together with sorting and mapping. It is very likely that this infrastructure can be developed in the near future.
Completely damage-free from saw to reel seems like an impossible mission at first, but can be addressed with proper planning. Most saw errors can be overcome with the proper substrate design. Sawing through the busline has been demonstrated for the regular FBGA package. However, the best results can be obtained when sawing is not conducted through any metal. Furthermore, metal pullback for the pads is an important feature to prevent any mistake in sawing through metal as a result of saw inaccuracy. Metal-defined target mark or fiducial is another important design feature that ensures sawing accuracy with respect to the CSP metal pads location. In other words, the substrate design should have robust design for manufacturing (DFM) features. Tradeoff Analysis Table 2 compares the attributes of singulated test versus strip test. Strip handlers should not limit the number of parallel sites to be tested. This number should only be limited by tester resources. Figure 5 shows the UPH curves for a Quad site-singulated pick-and-place handler vs. strip handling with four sites and greater. The chart speaks to the advantages of strip test.
Conclusion The integrated assembly and strip test of CSPs has been demonstrated in the development of CSPs at National Semiconductor Corp. The advantages described in this paper and the methods to achieve the strip test results have proven that the integrated assembly and strip test are reliable, manufacturable and cost effective for high-volume CSP production. Acknowledgements The authors acknowledge development partners from the Assembly and Packaging Group at National Semicon-ductor Corp., Singapore, our CAD and CSP groups in the Package Technology Group, our Test Group at National Semiconductor Corp., Santa Clara and the senior management for their funding and support.
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