By Wayne Moore
To paraphrase Sir Winston Churchill, final test is a riddle wrapped in a mystery inside an enigma. To the test community, there is nothing mysterious about the test process. But to the rest of the world, test frequently seems to be a black art. Vocal Minority Additionally, there is a small, but often vocal minority of IC test customers who firmly believe two things: First, packaged ICs need not be subjected to the extra expense of 100% final test; and, second, any parts that fail in the field should have been caught during final acceptance testing! As suppliers of extensive parametric, as well as functional test services, we don't believe that there is an unusual dichotomy to those seemingly contradictory positions. To many customers, the cost of test is still a slightly annoying adder to the real business of getting the device fitted into its plastic, ceramic or metal container so that it can take its rightful place on the PC board. And that place today is becoming smaller and smaller. The necessity of 100% parametric test on certain high-end parts is often forgotten until a major disaster occurs. When the finger pointing begins, it's often aimed at the test cycle, an area with which most packaging engineers are not overly familiar. (Did someone say design for test? DFT, despite dramatic attempts within the test community to make it part of the IC production cycle, is still a badly played anthem in most parts of the industry.) To the suppliers of test services who must buy the ATE systems, setting up a new system, for area-array test, for example, can be a bitter pill to swallow. ATE equipment is not cheap; prices for equipment to test microprocessors and/or advanced communications ICs begin at $1 million and rise skyward. Complicating the picture further is the inability of one sector of the semiconductor industry to speak in a terminology recognizable by all, typically sprinkled with acronyms. For example, unless you're a test engineer-or have some very specific reason to know-test terms like BIST (built-in self-test) probably don't mean much to you. Renovating the test area on the assembly floor often means making extra room for new test equipment, not simply replacing the older equipment. It is likely that the older gear will still find use among commodity products. Finally, after the diced ICs have gone through die attach, wire bond, molding, testing for opens and shorts, burn-in and then final test, to the customer's eyes these packaged and tested ICs don't look any different from the packaged ICs, several steps back in the cycle. With the acceptance of chip-scale packages, many of the things we learned about testing, particularly in test handling, become facts we have to re-learn. And just as we're becoming comfortable with testing CSPs, most CSP vendors are now talking earnestly about packaging at the wafer level. That, of course, will also mean testing at the wafer level, introducing a new paradigm for the IC designer and the test services vendor. Is the ATE provider, then, the winner in the race to close the IC test gap, shoveling buckets of money into his/her valise on the way to the bank? Unlikely. Although their equipment is priced in the eight figures, designing, building and marketing it requires a large, complex and costly infrastructure. A Needed and Irreplaceable Part As we enter 2000, we can only hope that the true worth of final test will finally be appreciated for what it is: a necessary and irreplaceable part of the semiconductor manufacturing cycle.
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