An Independent Journal Dedicated to the Advancement of Chip - Scale Electronics March - April 2000 Email the editor

Flip-chip assembly has become popular for laminate BGA single-chip packages, yet the technology has been slow to move into chip-scale packaging. The advantages of flip-chip assembly for devices with more than 600 I/O are well understood. Flip-chip assembly provides high-performance electrical interconnection, high-speed first-level attachment to the substrate, chip-size reduction for pad-limited chips, and heat removal from the back of the chip.

By Robert Crowley Contributing Editor

Many companies have investigated flip-chip-on-laminate CSPs to realize these benefits for chips with 100 to 200 I/O, but few have moved into high-volume production. Is this a case of using the wrong technology for the packaging problem or using the right technology before it is ready?

Companies such as Motorola and NEC have made considerable investments in flip-chip technology for laminate packages barely larger than the chip itself.

The technical issues related to process optimization, wafer bumping and material selection have been resolved, and the packages pass qualification tests. However, these packages have not moved into production as expected, and the primary reason is high cost.

For chips with 100 to 200 I/O, wire bonding remains less expensive. Once again, a technologically superior package has failed to replace a lower cost existing package. Note, however, that flip-chip on ceramic chip-scale packages have been in production for years by companies such as Matsushita.

The cost structure for flip-chip packages depends largely on the cost of the substrate and the cost of wafer bumping.

Low-Cost Wafer Bumping

Thin, laminate substrates with microvias and fine-line wiring still demand a price premium. Low-cost wafer bumping is becoming more readily available with a variety of solutions, including electroless nickel bumping, solder paste printing, solder electroplating and stud-bump bonding.

	Advanced packages are often marketed on technical superiority. Observations of many new package introductions suggests that new package technology will displace existing technology in two situations: where the new package allows for overall system-level cost reductions, or where the packaging requirements cannot be met by the existing package technology.
High-performance CSPs will use wafer-level and flip-chip assembly.

It remains difficult to see how flip-chip packages will ever cost less than wire-bonded packages for relatively simple chips. Changes in packaging requirements, however, will inevitably lead to a demand for more flip-chip CSPs. Increasing clock rates and increasing heat dissipation will make plastic-encapsulated wire-bonded packages unsuitable for many applications.

Two Options

Two packages styles can help here: flip-chip laminate CSPs and wafer-level CSPs. While small chips with few I/O are natural candidates for wafer-level packaging, chips with more than 100 I/O will move more towards the flip-chip laminate CSP.

As ICs are designed for flip-chip assembly from the start, the cost of bumping will decrease, because the redistribution layer can be incorporated in the final metal layer instead of being added in the bumping process. Combine this with cost reductions in microvia substrates, and the cost premium for flip-chip packages will decrease. It appears that flip-chip laminate CSPs are the right technology for applications that need the performance, and these CSPs were developed before the true market demand developed.