An Independent Journal Dedicated to the Advancement of Chip - Scale Electronics March - April 2000 Email the editor

In the eyes of a two-year-old, a dog is any furry creature that walks on four legs. The single descriptor dog finds general-purpose use around the family, covering a full menagerie including dogs, cats, mice, horses and even baby sisters. As the toddler matures, he learns that it is not as cute as it once was to call his little sister a dog. With maturity comes the ability to distinguish subtle differences between members of a class. While wafer-level packaging is still in its infancy, it includes a growing range of tech-nologies. Now, at several years of age, it is time that we begin to differentiate between the various types and their applications.

By Dr. Tom Di Stefano Contributing Editor

The "one-size-fits-all" approach fails in this area where different requirements drive each application segment. Rather than one wafer-level packaging paradigm, we find several approaches in which each one is shaped by the dominant factors driving the segment. We also learn quickly that not all wafer-level packages provide equivalent function.

Certain technologies are moving rapidly to fill specific applications while others are years away from the market.

Dallas Semiconductor and National Semiconductor, for example, already have wafer-level packaged chips on the market, while those pursuing more demanding and complex applications are still in the laboratory stages of development.

Among the first to use wafer-level packaging are low I/O applications, because they require no drastic changes to the infrastructure for packaging or system assembly. Most are using adaptations of mature flip-chip technologies that are finished into a surface mountable IC.

Reliability requirements are easier to meet on these small chips than on the larger memory or processor ICs. Thermal mismatch is less important because of the small chip size. Designing with these chips is straightforward, even at a grid pitch of 0.5 mm, because circuit board wiring is adequate to wire the low I/O footprints.

Early applications include integrated-passives, power-conditioning chips and discrete devices.

Development Activity

A considerable amount of development activity is aimed at memory chips for which the challenges and rewards are greater. The cost saving of wafer level production is driving this activity to lower package cost, and to more efficient burn-in, test and production logistics.

Even with this high level of activity, we are several years away from full wafer-level production of memory chips, because of technical issues in reliability, wafer burn-in and infrastructure. Early prototypes from Fujitsu, OKI, TIJ and others show promise for the future, with more to follow.

The memory sector is particularly important to watch, since it has the ability to set protocols and standards for the industry. Watch for solutions to wafer burn-in and test that can be used in ASICS and processors. The protocols that evolve for high volume memory, moreover, will influence other sectors, helping them to resolve issues in handling, logistics, reliability and shipping.

Benefits

Processors and ASICS stand to reap the greatest benefits from the move to wafer-level packaging, but they are not leading the pack because of a range of technological problems.

In these high-performance chips, power and ground distribution in the package promises higher performance, while reducing the need for higher pin count.

The package is also being considered for critical intra-chip wiring of clock trees and other RC limited on-chip networks. High-density interconnect capability is needed to satisfy these requirements, in addition to the other challenges of wafer-level packaging.

Building this entire infrastructure will take time.

We can understand this field better by considering separately the applications in low I/O, passives, memory, processors and others as they emerge.