This patent uses basic TAB technology that has been modified to produce CSPs. In addition to using a continuous process, this approach does not require the IC to be bumped. Two prior art examples are discussed; the first is a conventionally bonded TAB device which employs a large fanout and requires an extensive PWB area. The second example uses a ceramic substrate to form a chip-scale package, but this approach is difficult to automate. TAB Interconnect Single-metal-layer TAB tape is etched to pattern the copper layer, which can be bonded to the TAB film (a polymide) using any of several methods. The inner electrode hole on the topside of the film (see illustration) is formed by mechanical or laser drilling or by alkaline etching. The film properties that are important are the ability to withstand both wire bond temperatures and alkali etching if this method is used to form the via holes. After etching, the topside via is formed by plating Cu, Ni or Au up to the surface of the film. A bump is formed on top of the via using wire bonding or plating methods. Wire bonding can form balls of Au, Cu or solder. These wire bond bumps are fused to the via columns. Bumps can also be formed by plating. A layer of epoxy resin is applied over the conductor pattern on the bottom side of the tape. Holes are formed where the external bumps are to be located, and each of the holes is filled with solder applied using a wire bonder and solder wire. Chip Attach The unbumped chip is attached to the bumped tape using a hot bar, pulsed heating or by employing single-point bonding. Single-point bonding is preferably performed thermosonically to lower the required bonding temperature. Where solder is the bump material, standard reflow techniques can be used, with the solder automatically correcting for any misalignment.
The chip is sealed by transfer molding, potting or a combination of methods. In one method, the space between the chip and the TAB frame is filled with an epoxy resin while the back area is filled with a silicone resin. The key to having a high yield sealing process is to ensure that the encapsulant forms a strong bond to the polyimide film. This can be done by ion etching the film, immersing the film in a hot solvent or alkaline solution and/or mechanically roughening the surface. To improve the heat dissipation capability of the device, the back surface of the chip can be left exposed for later attachment of a heat sink or a heat spreader can be bonded to the die and then held in place with the seal resin. Additional thermal bumps can be provided on the face of the chip to connect to pads on the TAB frame. These pads are bumped to form thermal vias to the PWB.
|
