By Steve Lerner and Claudio Truzzi, CS2, Zaventem, Belgium Wireless communications have recently become the dominant sector of the electronics industry in Europe. Smaller size and higher system performance at lower cost, are the key requirements of this sector, pushing the envelope of advanced packaging technologies. In addition, semiconductor suppliers and packaging foundries are responding more rapidly to the needs of equipment manufacturers who face shorter product life cycles, requiring quicker time-to-market. In 1999, more than one mobile phone out of two sold worldwide was made in Europe (Ref. 1), and the cellular/PCS base-station equipment sector is also dominated by European companies. The requirements from this sector, in fact, have become the major drivers influencing industry trends. New Solutions This article analyzes how these requirements are stimulating new IC packaging solutions and how the electronics industry supply chain is being reshaped to cope with those needs. In terms of new solutions, portable electronic devices with slim designs require very thin package constructions. Currently, the industry targets package designs of less than 1.2 mm overall height, measured from the upper side of the package down to the surface of the underlying PWB. Chip-scale packages, or BGAs based on flexible tape or very thin laminate substrates, offer the potential to deliver solutions to these challenges. Traditionally, flex has been the most widespread CSP-substrate technology, accounting for about half of all CSPs. (Ref. 2) This substrate's market position has been due largely to its high circuit density. Today, however, the availability of very thin laminate substrates with improved design rules has enabled the manufacture of ultra-thin, laminate-based BGAs (0.9 mm). The telecom sector in Europe is rapidly adopting this ultra-thin, laminate-based package option because it provides better board-level reliability than flex. Figure 1 shows the results of a Finite Element Model (FEM) analysis of die stress for BT-resin laminate BGA and flex-based BGA. The model is a 12 mm X 12 mm package with an 8 mm X 8 mm die. The thickness measures 1.1 mm for both packages. Maximum solder ball stress for flex-based BGAs is 54% higher. Maximum substrate deflection for flex-based BGAs is 70% higher. Analyses performed on other package sizes deliver comparable results.
Additionally, the flexible nature of flex-tape substrates makes it difficult to handle them during manufacturing-each process step has its own mechanical and space requirements for holding the flex tape and handling it properly, considerably lowering the range of assembly options. In contrast, rigid laminate substrates do not suffer from this limitation and can be processed using the existing assembly infrastructure, which enables a better cost/performance ratio. Stacked CSPs Stacked CSPs, where multiple die are mounted on top of one another in a very thin package (less than 1.4 mm), offer a good solution when the ICs can share the same signals, such as address and data bus for Flash and SRAM memories. This solution is being rapidly adopted by the telecom sector. A proposal for an industry-wide standard for stacked multi-chip packages (MCPs) for SRAM and flash memory products, (originally drafted by Toshiba, Fujitsu and NEC), is currently under review by JEDEC, the standards organization. For memory, two or more chips in one package minimize package size and assembly area, reduce board area and weight and will support higher memory densities in the future. This pin assignment solution supports a range of densities from 4 Mb-128 Mb flash memory and from 1 Mb-128 Mb of SRAM. To meet the needs of the telecom sector, the overall thickness of the MCP will have to be reduced to less than 1 mm. Lead-free Packaging Lead is one of the most extensively used chemical elements on earth, with applications in batteries, roofing materials, fuel additives, board assembly and packaging. Electronic packaging primarily employs eutectic Sn63Pb37 solder. Some 50,000 tons are used annually worldwide. Very recently, the move towards lead-free assembly and packaging in Europe, originally scheduled by EU directive for 2004 (Ref. 3), was dramatically accelerated by the requirements coming, again, from the wireless communications market sector. This market will require lead-free packages by the year 2001. Alternative alloys based on different combinations of a variety of metals, such as tin, silver, copper or bismuth, almost always require a higher peak temperature during the reflow profile. This higher temperature affects warpage of the interposer and accelerates the formation of intermetallics, which could lead to brittleness. The use of Pb-free alloys inevitably modifies the grain structure of the solder balls, the combination of phases, the defects, morphology and distribution of the phases, and the intermetallic layer characteristics, as well.
The substrate body is realized by injection molding and includes a die cavity and studs that replace the solder balls. The body is then fully metallized using standard Cu/Ni/Au plating techniques and patterned with a laser-direct structuring technique, by which 50-µm spacing between the traces are ablated to create proper connections between the bond fingers and the studs. Die-up and die-down options are available. System-in-a-Package Most electronic systems can be partitioned in different clusters. Clusters that are critical, in terms of interconnectivity requirements, thermal management or signal integrity, can be assembled and packaged as separate functional blocks. To be cost effective, these units must be small (typically less than 1 inch square), possess a low component count (generally less than five active components), be manufactured using the standard infrastructure and be "transparent" to the PWB assembler, i.e. they must be assembled on the board as any other component. The board assembler should consider these functional blocks as just another component, regardless of the number of active devices inside. This approach is emerging for the implementation of RF functions for front-end applications. Few RF ICs with very limited pincounts and a large number of passive components for filtering and biasing purposes typically realize these functions, however. It is now possible to implement these functions in single packages by integrating the passive components into the package itself. This approach is known as system-in-a-package (SIP). As opposed to system-on-a-chip (SOC), the SIP approach is more easily achieved and in many cases provides more cost-effective solutions with a shorter time-to-market. Probably one of the strongest points of the SIP approach is the capability of removing large numbers of discrete components by integrating them into the substrate itself. Passive components can be integrated in different substrate types: laminate, ceramic, silicon or glass. Customer Relationship Until recently, most semiconductor manufacturers were not too concerned with the parasitic effects of the package, but this attitude is changing rapidly. The 1999 International Technology Roadmap for Semiconductors (Ref. 4) shows that to fulfill the main requirements for next generation, high-performance ICs, new and complex packaging technologies will have to be implemented. IC packaging has become big business, and it's becoming a complex and costly one, too. As a result, semiconductor vendors and fabless companies increasingly rely on silicon foundries for the front-end part of IC manufacturing and a packaging foundry for assembly, packaging and test. Today, the introduction of new technologies in semiconductor processing is increasingly influenced by market conditions, after technology roadmap issues. Smaller size and higher system performance at lower cost, are the key requirements of the wireless communications industry in Europe and elsewhere, pushing the envelope of advanced packaging technologies. In addition, semiconductor suppliers and packaging foundries are responding more rapidly to the specific needs of application equipment manufacturers who face shorter product life cycles, requiring quicker time-to-market. Customization One of the main reasons the industry is focusing on area-array packaging technology (such as BGAs) is because this technology has the ability to deliver custom or semi-custom packaging solutions. Apart from the possibilities they offer in response to the ITRS roadmap, they give IC designers the option of being in control of packaging development due to the interconnection and pin location flexibility, instead of being forced to a given, standard package format. Chip/Package Site Synergy Custom packaging solutions will be the new packaging trend if they can be delivered with very fast cycle times. This implies that the assembly contractor should maintain a close relationship with the customer. First engineering samples should be returned to the customer in a matter of days, and production time should be short enough to compete with standard packages and just-in-time market demands. Today the chip designer and packager are now interacting in the course of the chip development. This is in contrast with standard off-the-shelf packages, where chip designers are not very concerned about the packaging part of the process. In this new scenario, package design and characterization has become an integral part of the chip development flow.This tight loop between packaging foundry and IC developer calls for a site synergy between both parties. Clearly, the need for advanced local packaging services is growing, especially in Europe, with its strong wireless communications and automotive industry base. Locally available, highly automated but flexible assembly resources enable semiconductor foundries not to miss the correct market entry point. One may wonder about the higher costs that could be incurred when using custom or semi-custom packaging solutions. Although they are subjected to more frequent NRE costs than standard packages, this will be largely compensated by their relatively short production cycle time. According to McKinsey and Company, a longer production cycle time causing a late entry in the market, more strongly influences profits than excessive production costs or unit costs (Ref. 5). To quote McKinsey, "Profit losses due to a 6-month shipping delay can amount up to ten times the loss due to a 50% unit cost overrun." System Integration One way to answer the growing need for packaging miniaturized wireless electronic systems is to integrate different sub-assemblies or clusters of components into one package. Examples of such clusters are DSP with SRAM, GSM chipsets and baseband modules for wireless LAN. The boundaries that have traditionally existed between IC design, system design, component handling, board manufacturing, assembly and test are gradually disappearing. The effects of the various functions and blocks have to be taken into account from the early development stages. This evolution towards "integrated" system integration is perhaps one of the most important evolutions in the development of new generation ICs in the past 25 years and has been included in the latest versions of the roadmaps. In the longer run, it will reshape the way business is done in the semiconductor industry. The Next Step European packaging foundries focusing on area array services are already hitting the cutting edge of the BGA roadmap (Figure 3), as defined by the JEDEC standards: Ultra-thin Fine-pitch BGA (UFBGA, maximum 1 mm thick, JEDEC STD 95-1) are now qualifying for the telecom market.
This approach packages the die entirely at the wafer level by fabricating packages for all the ICs on a given wafer. Today, memories, ASICs, linear electronics and glue logic are the preferred candidates for WLP technologies. On the longer term, the ability to integrate passive components into the package (especially for RF front-end applications), will pave the way for the integration of opto-electronic components, passive structures and MEMS in low-cost packaging. This approach, frequently referred to as Integrated Packaging (IP) or system-in-a-package technology, will represent a serious alternative to SOC. IP technologies have the potential of providing solutions to the most important challenges faced by SOC technologies: cost, time-to-market, and legal issues. Summary
While flexible substrates have been the choice for CSPs, and near-CSPs, because of the high circuit density flex circuits permit, the recent availability of very thin laminate substrates has enabled the production of BGAs as thin as 0.9 mm. Due both to its footprint and board-level reliability, the European telecom sector is embracing this laminate-based package format. References 1. R. Henkel, "Finland's Nokia Extends Lead in Booming Cellular Market," Semiconductor Business News, Dec. 16, 1999. 2. BPA Group Ltd., "Technology Watch Report," December 1998. 3. Directive 76/769/EEC, EU second draft WEEE (Waste for Electrical and Electronic Equipment), July 1998. 4. International Technology Roadmap for Semiconductors, 1999 Edition, SEMATECH. 5. H. Koyama and R. Van Tassel, The McKinsey Quarterly, Number 3, 1998, pp. 142-153.
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