First, let's look at an extremely simplified IC test flow. After a wafer is processed through the fab, it is typically tested to a relatively loose set of parameters at wafer sort test. This testing will usually relax most of the AC parameters, such as frequency and propagation delay, while attempting to test most DC characteristics thoroughly. The next test step is post-assembly package test. This test is usually the one that stresses AC parameters, as well as any functionality that was difficult to test at wafer sort. This overly simple test flow has already lost favor in the commodity memory market, due to the fact that it doesn't maximize the package test yield. Why is this important in the DRAM manufacturing segment, where the package cost is fairly minimal? There are two reasons: First, DRAM makers are concerned about those few pennies wrapped-up in the failed packaged units, due to the extreme level of price/cost competition in the memory marketplace. The second reason is that memories are tested in parallel at all levels of testing. Parallel testing requires that the yield be as high as possible, and that the speed or other performance binning be as consistent as possible to ensure efficiency. That issue may alter the way a CSP test process is designed, especially if the devices are non-memory ICs. CSP assembly is particularly suited to handling the devices in a strip, matrix or panel of devices. This panel is a ready-made carrier to move multiple devices through a parallel test system-handler combination. Batch handling will drive the manufacturer toward parallel test even more strongly than in the past, since it may be possible to move 50-100 devices in parallel. As a result of this efficiency, the average CSP device will now have the same yield and efficiency issues that have been driving DRAM testing for some time. Correlation Achieving a high level of correlation from wafer sort to packaged test may require some manufacturers to add at-temperature test to their wafer sort equipment. At-temperature testing requires wafer probers which are equipped with special "hot and cold" chucks or wafer stages. Additionally, much greater characterization work may be needed to ensure that the relationship between fab process parameters and the final performance of the devices is well understood and guard-banded. Probe Cards Special high-performance probe cards may be needed to achieve full performance testing at speed and with full specs for analog signals at wafer test. This strategy implies that the high-performance test equipment will be used at wafer sort, and that a lower cost, lower performance ATE choice may be made for final test. In fact, the first drive to ATE that fulfills this niche has already begun. I expect that ATE capable of 3,000 or more channels with the capability to efficiently test >64 devices per station at $10K cost/site is going to arrive within the next year. These new machines will offer full DC and minimal AC specifications. It will be interesting to see how this affects the overall ATE marketplace.
|
