The explosion in demand for smaller and lighter handheld devices-such as cellular telephones, PDAs and camcorders-has sparked a flurry of new products in the IC packaging world. Although they are not exactly new, stacked packages have become a beneficiary of this handheld explosion, with these packages expected to grow from 130 million units in 1999 to more than one billion in 2004. Vertically Stacked The common thread among stacked packages is that the die are vertically stacked, rather than being placed side by side, as in a typical multichip package (MCP). Stacks can be two or more die in a single package or individual packages vertically stacked. Stacked TSOPs are an example of individual packages vertically stacked, while stacked CSPs vertically stack individual die within a single package. Stacked CSPs may feature flexible or rigid substrates. Many stacked packages integrate memory devices, such as flash and SRAM, but ASIC devices and MCMs have been integrated in stacks, as well. Most of the early stacked packages were designed for low-volume applications, such as military and aerospace. However, the stacked packages that are driving the volume projections cited combine a flash chip and an SRAM chip for the cellular handset market. Package Design There are several methods of designing a stacked package. The most common is to wire bond each die individually to the substrate below, providing each die an exclusive electrical link to the substrate. Another method is to add redistribution layers between the die so that the electrons run up and down through the entire stack. As a result of this method, all the die are electrically connected. In either case, chips placed in a stack must run cool, since attaching a heat sink in the middle of the stack would be difficult. A variation of the wire bonded stacked package is to place a single die within the stack with the flip-chip process. When flip-chip is employed, the die flipped can be either the bottom or top die; both approaches have their merits. Flipping the bottom die provides a direct connection to the substrate and enables the IC to operate at a very fast speed. The other alternative is to flip the top die to eliminate the long wires. Interconnection for that die, then, is through the die below it, which is wire bonded to the substrate. When both die are wire bonded to the substrate, a 0.5 mm-1 mm shelf must be exposed around the edges of the die to allow for the wirebonds to protrude from the top. Essentially, a die must be sufficiently larger than the die above it to allow room for the wirebond connections. If the die are too close in size, the bottom die must be flip-chip bonded to the interposer below. It is possible to have three die in a stacked package all wire bonded, but care must be taken to avoid wire wash and crosstalk. Sharp, the first company to offer a stacked package commercially, has a technique to accomplish this feat. JEDEC standards have recently been approved to help facilitate stacked packages as a standard product. Intel, Mitsubishi and Sharp designed their stacked packages around these standards; in fact, Mitsubishi and Sharp were the driving forces behind the implantation of the standards. NEC, Fujitsu and Toshiba have developed their own common pinouts, making them drop-in replacements for each other.
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