Current Issue An Independent Journal Dedicated to the Advancement of Chip - Scale Electronics March 2001 Email the editor

By Erin Yaeger, Loctite Corp., Rocky Hill, Conn., and Dr. George Carson, Dexter Electronic Materials, City of Industry, Calif.

Figure 1. CSP underfills encapsulate the gap between the CSP body and the motherboard.

While capillary flow underfills dramatically improve CSP reliability, their widespread use has been limited due to complex application requirements that restrict the integration of underfills into SMT assembly, and also complicate repair and rework.

Underfills are epoxy-based materials that flow into small spaces to fill the gap between the component (or die) and the substrate to which it is mounted. On CSP assemblies, failures typically occur at the substrate-to-ball interface or at the ball-to-package interface, where the solder ball cracks as a result of shock on the joint.

CSP solder ball connections are protected by underfilling, which minimizes the effects of stress and strain caused by CTE mismatch between the CSP and the motherboard or by board flexure during impact and vibration.

Prismark Partners, Cold Spring Harbor, N.Y., estimates growth in the CSP market through 2003 at more than 75 percent, with consumption of CSPs placed at 4.4 billion units for that year. If only a portion of these packages require underfilling, CSPs will be a significant market opportunity for suppliers of underfill materials and associated dispense equipment.

Capillary FCOB Underfills

Many CSPs (except those that are peripherally leaded), use preformed solder balls in place of solder bumps to provide interconnection, and do not require the use of an underfill in board assembly.

CSP underfills encapsulate the gap between the CSP body and the motherboard and are a low-risk approach to reinforcing CSPs for improved shock resistance and drop test reliability. Bending forces transmitted by the board during impact or vibration are distributed over the entire encapsulated area, which includes the solder bumps and the underfill material.

These materials must exhibit high adhesion. Both adhesion and reliability are improved by ionic content and an absence of voids during the capillary flow process.

A number of currently available underfill materials were originally developed as flip-chip underfills, but serve very well for CSPs. These low viscosity liquids are designed to flow quickly under a component by capillary action.

Quick Curing

Underfills designed for assembly-level flip-chip generally cure in five minutes or less at 165°C to form a hard seal with very high adhesion to both the CSP and the motherboard. Underfills that incorporate mineral fillers, such as silica, provide a CTE in the range of 18 to 35 ppm/°C and a modulus of 4 to 12 Gpa. These, however, are generally over-designed as CSP underfill materials.

Requirements for CSP reliability are motivating the development of new underfills designed specifically for these packages. Improvements in flow speed, cure time and cost are possible if sacrifices are made to the CTE and modulus properties of the cured material. Since they do not affect the failure modes of CSPs, these properties can be easily adjusted.

Capillary underfilling of CSPs is very similar to the well-recognized processes used for capillary flip-chip underfill. Employed in space-constrained applications, flip-chips are typically high-performance, high-I/O devices that rely on solder bumps to provide the needed interconnections.

For these devices, underfills are used to absorb stresses caused by CTE mismatch between the chip and the board. Flip-chip underfills are formulated to provide low ionic content, high adhesion, low CTE, and high Tg. Designed to permeate under the chip, these underfills flow void-free with appropriate process control during the capillary-flow processing step.

For capillary flow underfilling of CSPs, the package is first attached to the motherboard by stenciling solder paste onto the attach site, placing the CSP into the paste, and reflowing the assembly to form a metallic interconnection.

Capillary Forces

The assembly is now ready to be underfilled. Underfill must be applied close to the edge of a CSP to enable capillary forces to encapsulate the gap between the CSP and the board. The material is commonly dispensed in a continuous line along one or two edges of the CSP. Some time is then required for the material to flow beneath the package.

If a symmetrical underfill fillet (excess material that flows outside the CSP area) is desired, additional material may be applied along the remaining edges once the entire gap is filled. Self-filleting materials will form a fillet without additional dispensing.

Dispensing of capillary underfill materials requires specialized equipment to achieve the accuracy and precision required for high-volume assembly. At a minimum, the board manufacturer must reproducibly position successive CSP assemblies and apply a predetermined volume of underfill to the edge of the CSPs.

Heating the board or the underfill is a common secondary requirement, and accelerates the dispensing and flow of the underfill. Cure is usually accomplished in belt-style reflow or curing ovens, which can offer multiple lanes to improve throughput.

Capillary flow underfills do have some processing disadvantages, including the need for dedicated factory space, equipment and personnel, which may increase board assembly costs.

A "keep-out zone," devoid of other components, is required around the CSP to accommodate the underfill fillet.

Moisture from the board during cure can become trapped, leaving voids in the underfill. These voids, however, will not usually affect CSP reliability. Finally, almost all capillary flow underfills are permanent, making replacement of faulty components impractical.

Figure 2. After device removal, residual underfill material remains on the die site, along with solder on the PWB pads.

Fluxing (No-Flow) Underfills

Fluxing, or "no-flow" underfills are an attempt to make underfill processing more compatible with conventional surface mount assembly processes by eliminating the dedicated oven required for curing.

A fluxing function incorporated into the underfill combines the CSP attachment and underfill cure processes. Similar to capillary flow underfills, fluxing underfills originally developed for flip-chip are applied to CSPs with little or no modifications.

Fluxing underfills are different from capillary flow materials in several ways, including viscosity, which is substantially higher in materials for fluxing. Since particles in the underfill will generally impede essential contact between the CSP solder balls and the attach pads, fluxing underfills are unfilled, resulting in a higher CTE. The reliability of fluxing materials, however, is comparable to that of a capillary underfills.

Significant Challenges

The use of fluxing underfills on high-volume assembly lines poses significant challenges. Perhaps the greatest disadvantage is the inability to repair the assembly; defective units must be discarded.

A poorly characterized or controlled dispensing process leads to excessive defects and is capable of halting front-end assembly. Poorly controlled and badly characterized material or reflow processing may cause curing of the underfill prior to reflow, leading to solder joint defects. Moisture evolving from the boards during reflow promotes voids in the underfill.

Reworkability

In the past, the application of underfill meant that a device could no longer be reworked or repaired during manufacture or in-field service, a fact that hindered the widespread use of underfill materials. Reworkability is required for circuit card assemblies with CSPs that fail during final test or are returned from the field. Many such electronic devices contain PCBs that are too expensive to scrap because a single bad chip cannot be repaired.

New generations of reworkable snap-cure underfill are now available that allow the CSP to be reworked and replaced, even after underfilling. Chemically different from other underfill materials, reworkable underfills are designed to break down when heated to solder reflow (rework) temperatures.

The rework process can actually be divided into three parts. First, the defective device is removed from the board during what would be a typical rework cycle.

After device removal, residual underfill material remains on the die site, along with solder on the PWB pads. As with the rework of non-underfilled packages, solder must be removed to eliminate the possibility of any pad-to-pad solder shorts, and leave a consistent, thin layer of eutectic solder for adequate wetting of the new CSP.

Figure 3. When some reworkable underfill materials are employed, the site is cleaned of solder and adhesive residue using a high-speed brushing technique.

Some reworkable adhesives need not be completely removed from the site. Other underfills can be completely cleaned from the site after solder removal, using a high-speed brushing technique without damaging the die site or pads, as shown in Figure 3.

After site cleaning, a new package can be attached to the board and underfilled. This rework process can be performed either in the manufacturing rework area after testing has shown a chip to be defective, or at a repair facility after a defective board is received from the field (Figure 4).

As with any new process, reliability cannot be sacrificed. The goal for an underfilled CSP is to preserve thermal cycling reliability and improve impact and vibration reliability. Drop and vibration testing by several sources has shown that reworkable under-fill materials exhibit reliability equivalent to that of traditional underfills and superior to the reliability of many CSPs with no underfill. Thermal cycling reliability is equivalent to that of a CSP without underfill.(2, 3, 4)

Future Developments

The impending development of underfill materials that are pre-applied to the CSP prior to board-level assembly will eliminate the uncertainties and imprecision of liquid underfill dispensing, a concept most often associated with wafer-level packaging.

The ideal pre-applied underfill is applied and stabilized at the wafer level. Application before bumping requires compatibility with the bumping process. Application after bumping must occur without coating or damaging the bumps, and the material must survive the dicing process without retaining silicon splinters and remain essentially unchanged for at least six months at room temperature.

The process for attaching the coated die to the board and finally curing the underfill will depend on the nature of the interconnect (solder, gold, anisotropic conductive film (ACF), isotropically conductive adhesive (ICA), etc.); however, restricting the technology to solder-based, reflowed interconnects seems unduly constraining.(5)

Lead reduction efforts throughout the world will likely result in solders that melt at temperatures significantly above that of eutectic lead-tin solder (183°C). If new lead free solder alloys do not possess the strength, toughness, or fatigue resistance of lead-tin eutectic solder, underfills will be required to maintain the reliability of the assembly. This will affect the nature of CSP underfills in several ways.

Very-fine-pitch CSPs do not yet require the same level of underfill as coarse-pitch flip-chips. Tomorrow's fine-pitched CSP's will almost certainly bring forth unforeseen requirements. These demands may include lower cure temperatures to accommodate new interconnects or board types, adhesion to novel CSP passivations or board metallizations or new reliability requirements.

Figure 4. This figure illustrates, from left, defective device removal, board cleaning and new device placement.

References

1. P. Elenius and H. Yang, "The Ultra CSP Wafer-Scale Package," Proc. HDI International, Tempe, Ariz., Sept. 15-16, 1998.

2. N. Hannan et al., "Development of CSP Reworkable Underfill and Rework Process for High Volume Production," Proc. APEX 2001, San Diego, Calif.

3. N. Hannan et al., "Qualification of Reworkable Underfill for Improved Manufacturability of CSPs," Proc. APEX 2001, San Diego

4. H. Peng and P.W. Johnson et al., "Underfilling MicroBGAs," Proc. Conference on High Density Interconnect and Systems Packaging, Denver, Colo., April 2000, pp. 134-140.

5. K. Gilleo and D. Blumel, "Transforming Flip Chip into CSP with reworkable wafer-level underfill," Proc. Pan Pacific Microelectronics Symposium, Oahu, Hawaii, February 1999, pp. 159-165.