By James Healy, ASAT Inc., Fremont, Calif.
Final test has changed dramatically over the decades, and yet the basics really have not changed very much at all, for reasons we'll explore shortly. The most common test method today employs a general-purpose (GP) tester, which closely simulates the physical environment that a device is subjected to in the field. (A variety of ATEsystems are shown in Figures 1-3.) Additionally certain defects can only be found by functionally testing the entire chip at speed. Unfortunately, functional testing is the most expensive way to test. In the beginning there was a digital tester for logic devices, an analog tester for analog devices and a memory tester for memory devices. As chip designers mixed digital and analog functions on a single chip, and embedded memory as well, devices would often have to be tested on all three testers. Employing this "triple insertion approach" proved to be an extremely costly proposition. Moreover, it would not always result in a thorough test, since faults with synchronization between on-chip circuit blocks were not always detectable. To solve these problems, ATE companies began constructing testers that were more general-purpose in nature, which incorporated many analog test functions into the digital tester. General Purpose Test Systems Testing the embedded memory further complicated the design of these GP testers. Either hardware or software was then needed to execute long algorithmic memory test patterns. At times, in fact, the memory nodes were not accessible, resulting in a challenge for the tester programmer. Faced with these complications and increasing test costs, chip designers developed many on-chip self-test schemes, such as boundary scan and Built-In-Self-Test (BIST). Both schemes fall under the category of "design for test" (DFT). The simplest scan designs partition re-configurable internal logic into long shift registers so a tester can serially scan in test vectors. The partitioned logic is then clocked and the output response is captured for comparison. BIST, on the other hand, is based on internal algorithmic generation of test vectors to "self-test" the partitioned logic, with the compacted results verified by a tester. For today's complex System-on-Chip (SOC) devices-which incorporate digital, analog and memory-BIST is becoming more prevalent because it does not require a lot of silicon (usually under 10K gates are sufficient). BIST has also become essential for testing the embedded memory. Structural Testers Testers designed specifically to work with test functions embedded in the chip are called structural testers. These optimized testers offer the advantage of being much more cost-effective than the GP tester, since they are less complex and require fewer pins. Most hard "stuck-at" faults can be detected with the combination of DFT and structural test. Unfortunately, if too many chip sections are tested independently, a GP tester may still be required to insure system-level integrity. Once it is proven that DFT coupled with a structural tester can in fact detect speed failures then a single low cost tester strategy could be employed. Until then a multiple tester strategy is required. Long slow-speed tests are performed at probe with a low cost structural tester. Shorter high-speed tests are performed at final test with the GP tester. Since fewer GP testers are needed, overall test could would be reduced. In a personal communication, Clyde Armstrong, CEO of Inovys Corporation, which makes structural testers, reported, "Interestingly, with the growth of DFT, less and less of the speed and functional capability of the GP tester is actually utilized in production to test the device." Although structural test techniques may reduce the number of GP testers required-eventually rendering them obsolete-the validity of test still must be proven. Finding all defects on complex designs requires multiple test techniques. As voltages drop, speeds increase and designs become more complex. The incorporation of DFT techniques is required even when functionally testing. At-speed functional testing is still the highest quality test, but, as device speeds increase, can GP testers keep up? Strip Testing Test costs can also be reduced at final test by selection of the appropriate test handler. Gravity-feed handlers are giving way to strip handlers, because strip testing appears to provide the lowest cost per tested unit and the highest reliability in contacting. It can result in increased first-pass-yield, eliminates re-test, and there are no tubes or trays to handle in the production flow. Fast changeover between package sizes, and the versatility of strip handlers, allows handling for most package types, including leaded, leadless and ball grid arrays (BGA), further reducing test costs. Strip testing also accommodates highly parallel test sites making it easier to balance parallel testing with test time and available tester resources. Benefits include better factory floor utilization.
A typical strip process can accommodate up to 20,000 units per hour, equal to 5-10 conventional tester/handler combinations (Figure 4). Another cost benefit is better test statistics from the strip map, which identifies marginal test sites and even traces problems back to die attach, wire bond, or molding.
Subcontract Testing Because IDMs (integrated device makers) test the majority of their assembled devices internally, final test has become a strategic opportunity and an asset for many assembly and test subcontractors. Full turnkey test support is also offered by many packaging foundries. Although subcontract testing has the same economic benefits as package assembly, often for security reasons or because test is considered a strategic advantage, final test is kept in-house. Test can reveal the internal workings of the chip, a disclosure usually considered proprietary. In other cases the chip maker feels that the subcontractor has limited test knowledge. The IDM may also believe the outside test vendor incapable of resolving test problems, because they do not have IC design knowledge. This results in a Catch 22 situation. If and when DFT and structural testing become more prolific these arguments may dissipate. Conclusion DFT does reduce test costs by reducing the number of GP testers needed for final test. On the other hand, if the device is designed to follow a specific set of DFT design rules, then a structural tester designed with a standard interface to communicate with the DFT structures may result in a single tester approach. When coupled with strip handlers, a further reduction in cost-of-test will be realized. IDMs may then be more inclined to subcontract final test, where they will enjoy additional savings. The cycle over the years has been from GP testers to more focused or dedicated testers but inevitably back to the GP tester. Today's SOC designs incorporate every conceivable type of design (analog, digital, memory) on single piece of silicon or in multiple pieces in the case of SIP. The delineation between logic, memory, and analog chips at this point is unclear, making it almost impossible to have a test strategy based on a non-general purpose tester. Real-World Problems The only way to deal with the real-world problems of the test floor is to spend more on GP testers, since quality problems must be avoided at all costs. This said, final test has changed dramatically in terms of its complex level of sophistication; yet it really has not changed at all, in terms of the approach needed to solving the ATE dilemma.
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