By Gil Olachea, Flip Chip Division, Kulicke & Soffa, Phoenix, Arizona
The semiconductor chip is at the electronic mercy of an "interconnect sandwich" created by the lead-frame/ substrate (BGA/CSP) and wire/bump connection. This first- and second-level interconnect system creates the means by which the electronic end-application (a PDA, for example) and the chip attain functionality with control and reliability. Designing and manufacturing IC packages (let alone fabricating semiconductors) is a surprisingly complex activity. The great number of production steps, material sets, tolerances, types of equipment and hardware, requirements for customization, short-runs, etc., must operate in concert. Costs can and will skyrocket if the orchestrated "tune" is akin to the output of a plastic kazoo. As Easy as 1, 2, 3 The primary productivity "hits" are anything that diminishes yield, increases costs, decreases throughput or compromises reliability. The following items are categorical "buckets" representing common productivity killers: 1. Bond pad issues 2. Leadframe or substrate compromises 3. Design changes 4. Wafer dicing 5. Thin and thick wafers 6. Special processes 7. Material sets and process variations 8. On-chip operational frequency 9. Chip backside properties 10. Customers, management, personnel and vendors Here's a brief review of each of these killers. Bond Pad Issues. This category is probably the most crucial, because it greatly affects yield, cost, reliability and throughput. Metallization, placement (pitch), contamination, proximity of active circuitry, quantity, etc., are never uniform from one vendor to another. They will, most certainly, always cause production delays.
A gating factor for this potential hotbed of problems is design (see item 3). Chip designers who obtain design guidelines from their IC packaging providers (a.k.a. subcontractors), and understand the practical limits of wire-bonding equipment, will find this information extremely beneficial (Figure 1). 'Nonstandard' Layouts This same important point is applicable to substrates and leadframes. This issue is exacerbated by designs that insist on arranging bond pads in ways that need special attention or programming of wire- bonding equipment to compensate for "nonstandard" layouts. Even with the greater flexibility of current wire bonders, productivity and cost benefits can be realized if design guidelines are adhered to and respected. Of course, if you have the budget to pay for non-standard processing, I am certain most packaging subcontractors will be happy to oblige. An additional issue worth noting is multimetal bond pad architectures. Aluminum isn't the only "flavor" any longer. With the advent of increasing chip and circuit speeds, creative solutions to propagate signals across chips are readily being introduced. Watch for Cu and low-k dielectrics to present a challenge to current productivity standards (Figure 2). Leadframe or Substrate Compromises. The leadframe (or substrate), is the equivalent of an automobile chassis, and the chip is analogous to the engine. Without a platform for the engine, the ability to transfer power and functionality to the wheels is defeated.
A properly designed substrate/leadframe with consistent, high-quality standards supporting the specs of the packaging assembly process is paramount for efficient transfer of power to the circuits (Figure 3). A poor design, or a low-quality product, can add cost in terms of yield, setup times and equipment throughput. Failing here with the leadframe/substrate will kill the IC. Design Changes. Initial chip designs for prototypes or first article inspection (FAI) units are rarely the same when they go into production. Understandably, the final design will have gone through a few changes-this is anticipated. What is not anticipated, or desired, is a mid-production chip design change that warrants re-programming assembly equipment software, new leadframe/substrate designs, FAI re-qualifications, or performance/reliability concession for "minor" design tweaks.
You can avoid these issues by utilizing manufacturing design guidelines. Wafer Dicing. Dicing is an often-overlooked process. Poorly done, dicing can cripple the reliable operation of a finished packaged IC (Figure 4). Cracks created by dicing blades can shorten the life of a packaged device (Figures 5 and 6). Poor attention and failure to understand this first-in-the-line process will reveal itself in every succeeding step.
No Equality Among Chips Not all semiconductors are created equally. Silicon is forged into wafers forming circuits that push electrons at megaspeeds. That's about the greatest similarity between the world's manufactured mass of semiconductors. From there, subtle variations in wafers are sufficient to demand careful attention to dicing parameters. These variations (grain structures, metalization schemes, dopants, diffusion processes, etc.) are inconsistent from maker to maker. Cracks created by "chattering" high-speed saw blades can be exacerbated during packaging and will quickly shorten the life of the device. Therefore, one set of dicing parameters is not adequate to address or satisfy the spectrum of wafers handled by any one packaging supplier. Thin and Thick Wafers. IC packages are precisely designed with tolerances that are held to fractions of a millimeter. When chips are too thick, the potential for assembly issues to surface is high. Areas that are impacted include wire bonding, dicing, die attach and mold/ encapsulation. Problems are magnified and will be especially evident with today's thin package technology (1.0 mm and sub-1.0 mm-thick packages). If the die exceeds the allowable thickness (>16-18 mils) the height of the wire loops will penetrate through the top of the mold outline. These exposed wires are obviously unacceptable.
Breakage At the other end of the spectrum, thin wafers (<8 mils) provide an extraordinary handling challenge. The potential for breaking wafers this thin-even with automated handling equipment-increases exponentially with each mil shaved off the silicon (or other material). The impacts are to throughput, cost and yield. Special Processes. It is not an unusual to semicustomize an IC's packaging. After all, everyone wants to have the best protection and interconnection for a carefully designed IC. Each special request or deviation from "standard" assembly specs, however, such as conformal or protective coatings, variable wire-bond pitch, mixed wire diameter, underfill, etc., will increase the time required to fulfill the request. In addition, the extent to which equipment will have to be modified to accommodate the request is a major factor in killing productivity. Special IC assembly processing must be tolerated in today's electronic market. Yet, with proper design, engineering, and occasional compromise, many special process requests can be accomplished with readily available materials, equipment, processes and by working within acceptable tolerances. Material Sets and Process Variations. This category dovetails with the previous one. Materials are specified to exacting requirements. However, when bonding wire, mold compound, die-attach epoxy, solder spheres, chemicals, temperatures, rates of speed, etc., vary from specified parameters, yield, reliability, costs and throughput are directly affected. This Productivity Killer category requires constant vigilance. On-Chip Operational Frequency(cies). ICs are being designed and developed for greater levels of operational frequencies. IC designers and microsystem engineers are very sensitive to slight variations that will cause system performance deviation. Trivial departures or manufacturing tolerances that are typically acceptable in broad product designs are intolerable in applications where RF and very high speed digital performance are necessary. Wirebonds can behave as antennae in these applications, causing bit errors or faulty data integrity characteristics. Today, "trimming" is performed to attenuate this phenomenon and influence high performance. Chip Backside Properties. Adding to the complicated and diverse topographies of the active side of wafers are their reverse planes. Some wafer designs employ a metal contact structure. More often, however, they use bare silicon. In any case, the finish is dependent upon grinding, polishing or etching processes. Variations in the finish (thickness, roughness, micro-cracking) can dramatically affect die-attach performance characteristics and impact yield and reliability. Customers, Management, Vendors and Other Personnel. Is this really a surprise to anyone? Our final category is a constant challenge to any operation. Poorly trained operators directly impact the quality and reliability of the packaging process. They may also have a huge affect on costs, if material waste/use is greater than tolerance. Vendors who do not fully understand and support supply requirements and delivery schedules absolutely destroy productivity. Engineers are always investigating means and methods of improving or fixing something. This "tweaking," when unnecessary, can impact cost and yield. It may also delay programs. Management and customers present a touchy situation. Too much or too little interaction influences and hinders optimal performance from operations. How does one know when too much exists? We have all been subjected to this situation often enough to know! The same can be said for too little. The secret is to have highly adroit, intuitive and empowered teams acting in the best interests of all concerned. Is IC Packaging a Compromise? Suffice it to say, it is truly a challenge to package ICs. Try as we may, the fact is packaging does not improve the operational metrics of semiconductor performance. Consider, too, that items such as metrology, die and wafer sizes, pad pitch and sizes, wafer warpage, semiconductor material (Si, SiGe, GaAs), dielectric, passivation and the like are in a constant state of conflict with effective and stable IC packaging. A Final Word Your list of productivity killers may very well differ from mine. If so, I'd like to hear from you to compare experiences. For the greatest number of years, the prime focus of the semiconductor-manufacturing sector was on the chip.
Making it smaller, more powerful, faster, more efficient and lower in cost, while creating high-value features and improving reliability, are but a few simultaneous success targets of the marketed chip in packaged form. Achieving these targets is not inherently guaranteed; compromise is usually necessary to optimize the delivered results. So far, however, the compromise has been working just fine.
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