Remember the old saying, "Be careful what you wish for-because it may come true?" It appears that we may well be moving down that road in IC packaging, where wishes do become realities. Just consider that dielectrics with low constants are replacing oxided silicon (SiO2) insulation layers on die. By reducing capacitance losses, these low-k dielectrics are an enabler of complex, gigaherz speed, high performance ICs. But low K dielectrics are also fragile, brittle. Furthermore, package-induced stresses may result in delaminating, distorting, and cracking them. Until now, better flip-chip underfills have been the focus of efforts to meet new package reliability demands imposed by the low-k era. Lead Counts Continue Climbing But flip chips and underfills are being increasingly challenged as lead counts climb into the thousands. There are three problem areas here: 1) underfill voids, 2) dense bump-to-die connectivity to handle more signal, power, and ground interconnects, 3) the low thermal conductivity of low-k dielectrics. Industry giant Intel has proposed a new packaging paradigm. This technology, called BBUL (Bumpless Build-up Layer), eliminates both flip chips and underfill while shortening the thermal path. Here are BBUL's features*: 1. The die is embedded in a bismalamide triazine (BT) laminate platform by routing a rectangular hole, which is secured by epoxy encapsulant. The BT is a platform for both the die and subsequent build-up layers. The die pads are in intimate contact with the first build-up layer. Microvias in the build-up layer reliably access die pads. 2. The new packaging scheme replaces 90-µm high, 90 percent Pb bumped with a 3-µm-thick copper pad; both are 80 µm x 80 µm. The resulting package stands only 0.9 mm off the board, half the thickness of the flip-chip package.
3. Comparative stresses among three alternatives were modeled: Organic Land Grid Array (Pentium 4 package) vs. 10-µm thick pad BBUL vs. 3 µm BBUL thick pad. The 3 µm pad wins big with minimal stress on die when cycled from 150°C to -55°C. 4. Underfill is eliminated, as are potential voids. That's an important issue when lead counts are climbing into the thousands. 5. The build-up layers consist of ABF (Ajinomoto Build-up Film) dielectric and electroless-electroplated Cu. The model has 3 layers of copper with ABF dielectric. Microvias are laser drilled to make contact between the die landing pads and theinterconnection layers.
More Advantages Other potential advantages include: 1. Routability benefits. Flip-chip density is now limited (e.g. 150 microns pitch) by substrate resolution. Contacting die landing pads by laser-drilled microvias relieves that constraint. Routability benefits derive from 100 µm or fewer microvias and lines in build-up constructions. 2. Increased productivity potential. Dispensing and curing underfill slows the production cycle. 3. The three layers of build-up copper may replace die layers. As scaling increases the resistance of lines on-die, moving them off-die improves performance. 4. Integrating the die to package level into the package. This reduces interconnection levels by one. 5. All-copper system. There are no solder or other metal interfaces, with all their reliability problems. 6. Alpha particle sources eliminated. Lead and tin are eliminated from die proximity in the package. 7. Low inductance. The inductance of embedded capacitors in the package is only 0.1 pH, an order of magnitude less than non-embedded constructions. 8. Integration. This technology offers the potential for ready integration of multiple electronic and optical components. 9. Significant improvements in electrical power performance. This attribute is due to the many access points and short paths. 10. Good thermal performance, a result of the high area to volume ratio. The Prize That's the concept, the prize. Today it's just a very attractive goal, an opening to a new stream of packaging development. Mike Busby (speaking at leave about this many words here) and others at Unistructure worked on a similar concept 10 years ago, and GE has a similar program. But endorsed and bankrolled by Intel, the $33.7 billion (2000) semiconductor leader, many others will follow the lead. Many will innovate in a new competition to address the many problems. By 2006, we may see the reality, perhaps in many forms, different from today's concept. As Ron Huemoeller of Amkor Technology Inc. points out, "The idea by Intel is a resurrection of older ones where a laminate structure with a cavity is milled or punched out. This structure should provide good performance if the manufacturability and yield issues can be effectively addressed." Issues to Be Addressed True of any breakthrough, there are potential problems. BBUL needs include:
Michael Knight, president of Substrate Technology, raises some practical implementation issues:
"With build-up technologies, each layer has a yield loss associated with it, and this loss is cumulative. "For such a packaging scheme to be cost-effective, it would have to be done in some sort of large area format. This means that even if you could find a defect on some of the die sites early in the process, you may still end up running the panel for yield. To do otherwise means scrapping all of the die committed to that panel," he adds. Also, in this scheme, the planarity of the die interconnect relative to ever other die in the panel is critical. With the variability inherent in die attach and encapsulation, we didn't see how a large number of die could be inserted into ganged cavities in such a way as the die pads would all be on the same plane.
Another Issue is CTE Mismatch CTE is another issue. For the fine feature sizes (via diameters, widths of lines and spaces), the CTE mismatch of the material set makes layer-to-layer circuit registration very difficult. The larger the panel size, the greater the challenge. Having said all of that, the Intel's idea has very clear advantages, and it is going to take a company with Intel's clout to sort out all the issues and obstacles to make it work. * R. Emery et al, Intel Corp., Novel Microelec-tronic Packaging Method for Reduced Thermo-mechanical Stresses on Low Dielectric Materials, Advanced Metallization Conference, Montreal, September 9, 2001
|
Copyright © 2002