March 1998
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The Impact of CSPs on Encapsulation Materials
Introduction
One of the more exciting recent developments in electronics has been the rapid emergence of chip scale packaging. The promise of chip scale packaging has captured the attention of virtually every semiconductor manufacturer in the world today. In the process of developing CSPs, a wide assortment of materials and interconnection approaches have been proposed, each intent on achieving the objective of reducing the dimensions of the package interconnect elements to chip scale. Because of their size, CSP technologies are driving the requirements for new encapsulation materials from a technology which has, heretofore, been relatively static. Formerly, one of the more prosaic elements of the electronic packaging process, encapsulant s have risen significantly in importance as silicon becomes and an increasing percentage of the finished package.The Role of Encapsulation
Normally there is a tendency to think of encapsulation only in terms of its ability to protect the IC physically from damage during assembly and use. However, on closer inspection one finds that there are actually a number of important roles encapsulants must play.
Figure 1- Semiconductor encapsulants serve a wide range of purposes.
Beyond providing physical protection, encapsulants also: protect the semiconductor die against contamination, provide a barrier against alphaparticle emissions, block out potentially damaging ultraviolet radiation, and protect the delicate wire bonds that make connection between the die and the package by providing a mechanical match in CTE between the wire and the encapsulant. A summary of the functions and benefits of encapsulants is provided in Figure 1. Given all of the roles that the encapsulant must play, it is vital that the selection of encapsulant be made with care. Determining what trade-offs to make in solving the many challenging problems that arise in packaging integrated circuits at near the size of the chip is not a trivial task.
The evolution of packaging, illustrated in Figure 2, has been driven steadily down a path toward chip scale by a continuing demand for miniaturization and performance. In this quest, it is asserted that the familiar benefits and traditional attributes of the package must be maintained in order to assure reliability. In conventional IC packaging, long, flexible leads provide reliable interconnection to the printed circuit to which it is attached. However, as packages continue to shrink, the ratio of encapsulant to the other package elements shifts to the point where the silicon IC becomes the dominate element. In order to accommodate increasing I/O counts under smaller packages, contacts are moved from the perimeter of the package to an array of contacts in the shadow of the chip. Further, as the leads shrink and become less compliant, the stresses generated at the leads increase, making them less reliable due to failure of either the package itself or of the solder connections to the PCB. Thus, the choice of method for ameliorating the
Figure 2 - The evolution of IC packaging to chip scale has placed ever greater demand on encapsulants.
Figure 3 - Decision tree for CTE mismatch.
Figure 4 - A complient package can expand and contract without stressing the solder attach balls.
stresses caused by differential expansion of the chip and its substrate is of paramount importance in failure prevention. The lack of space, under the chip, for traditional flexible links makes this task more daunting. As a result, the flexible link must either be provided within a compliant package or alternatively, the package must be bonded to the PCB by somewhat flexible solder joints.
Strategies tor decoupling the CTE mismatch between the IC component and PCB are represented graphically in the decision tree shown in Figure 3. Following the tree down to chip size packaging, it becomes quickly clear that one of two choices must be made. Either one must use a solder link that can deform plastically or one can make the package itself compliant. The compliant package stretches or deforms to match the expansion of the substrate to which it is mounted, and the flexible electrical link, which is embedded in the package, moves to accommodate the deformation of the package. In such a case the materials used in package construction must have a low modulus to allow the material to expand and contract with the substrate without stressing either the chip or the solder contact, as illustrated in Figure 4. The outcome of these two strategies are evident in the FEA models shown in Figure 5 which depicts the difference in distribution of strain in the two approaches caused by cooling devices from 150°C to -65°C. In the rigid package (right), the peak local strain in the solder ball exceeded 3.7% which will result in a predictable fatigue fracture. In contrast, the model of the compliant package (left) shows that a substantial portion of the strain is taken up by low modulus encapsulation, thereby reducing the strain component in the solder ball itself. In addition, the low modulus encapsulation reduces the strain transmitted to the face of the chip.
Figure 5- Finite element analysis shows thermally generated strain in a rigid package (left) and a complient package (right).
The strain on the solder ball, as depicted in the rigid package in Figure 5, can be reduced by use of a rigid underfill that couples the package directly to the substrate, creating the equivalent of a bimetallic strip. This warpage absorbs some of the strain which would normally have occurred totally at the solder ball.
Another important design point when creating a package using rigid encapsulants is the use of a balanced package construction. A balanced construction is recommended in order to prevent CTE related warpage.
Figure 6- Unbalanced packages constructed from rigid encapsulants can cause warpage.
With very thin package structures, significant new demands are placed on the encapsulation which now must hold to the die face by adhesive forces without benefit of reinforcement from the bulk of the package body. As a result stresses induced by expansion mismatches can cause edge cracking of the rigid material, delamination from the face of the die and popcorning due to moisture trapped in voids or delaminations.
Figure 7- The large CTE mismatch between the encapsulant and the die can result in a number of different types of defects as illustrated above.
Figure 7 illustrates these defect modalities. Additionally, for rigid encapsulation, it is necessary to match the expansion of the mold compound to that of the flexible link, in order to minimiz.e stretch fatigue in the link, whether solder ball or bond wire. Since it is impossible to simultaneously match both the die (CTE ~3ppm/°C ) and the bond wire, whether it be gold (CTE ~14ppm/°C) or aluminum (CTE ~22ppm/°C), the choice is usually made to match the wire. Stresses generated across the face of the die are somewhat ameliorated by a thin layer of flexibilized polyimide on face of the die. These concepts are illustrated in Figure 8.
Figure 8- For rigid packages, the CTE of the encapsulant is normally matched to the bond wire to reduce thermal stresses.
Obviously, the difficulties of stress reduction in rigid packages are exacerbated with increasing die size.
Encapsulation materials are available with a range of mechanical properties from very rigid to very compliant. Across the range of available encapsulation materials the CTE is largely determined by the modulus as shown by the shaded trend line in Figure 9.
Figure 9- The choice of IC encapsulation materials for either ridgid or complient packages is limited by several mechanism of thermally induced stress.
When summarizing the demands of CSPs on encapsulation materials, there are two distinct domains of operation, compliant encapsulation and rigid mold compound.
Typical rigid epoxy mold compounds have a CTE of 16 to 20 ppm/°C. To achieve this low expansion, the epoxy must be heavily loaded with fillers, such as silica. The rigidity or modulus of the mold compound is correspondingly increased with loading.
In order to achieve a compliant package, it is necessary to trade away the low CTE in favor of a low modulus which will provide compliancy, but which also must accommodate a properly designed internal flexible link. The band of available materials, shown in Figure 9, stretches from the upper left domain of soft, high CTE low modulus materials to the lower left domain of relatively rigid, low CTE high modulus materials. For flexible links encapsulated in compliant materials, the lead is strain relieved because of the lower modulus of the encapsulant material itself. This is because, the compliant material, although high in CTE, is aufficiently soft so as not to transmit strain to the wire or flexible link. The compliant encapsulant material also decouples the motion of the solderballs from the silicon, allowing them to move more freely in following the expansion of the PC.
In the domain of rigid mold compounds, several limits are set on the domain. The primary requirements in using rigid encapsulants are to: first, match the CTE of the wires and second, minimize shear stress on the die face. In the final trade-offbetween modulus and flexibility, the trade-off is typically made in favor of matching the CTE of the bonding wire.
The requirement for compliant encapsulation materials is driving the introduction of new and improved silicones and flexibilized epoxies. The silicone materials are particularly attractive because of their large range of thermal operation, their low glass transition temperature (which lies beyond the lower limit of -55°C) and their ability to bond reliably to silicon and to the aluminum die pads. Additionally, silicones are known to be very low in alpha emissions and are an excellent barrier to ionic contaminants. One final benefit of silicones is their unique ability to dissipate entrapped moisture easity without explosive outgassing as is experienced with less forgiving rigid materials. While silicones are the front runner, newer flexiblized epoxy materials are being developed that may challenge silicone's dominant position.
Summary
The electronics industry will continue its move toward ever smaller and more advanced packages, in which encapsulants will serve an increasingly important role. As packages move toward chip size, the demands associated with CTE mismatch will continue to rise in importance. Complaint encapsulants are expected to play an important role in meeting future CSP demands and needs and will likely constitute an outstanding opportunity for suppliers to a worldwide market estimated at two billion dollars. Look for the advances in both encapsulants and encapsulation processes to continue to accelerate.References
- Encapsulation Of Electronic Devices and Components by E. Salmon; Marcel Dekker, Inc., NY, 1987
Thomas Di Stefano is a founder and vice president of marketing at Tessera. He is a graduate of Stanford University, with a Ph. D in Applied Physics. Prior to founding Tessera in 1990, he was a senior manager in Manufacturing Research at the IBM Research Division in Yorktown Heights, N.Y
Joseph Fjelstad, a senior engineer at Tessera, has 25 years of national and international experience in the electronics interconnection industry. He was a consultant in electronic manufacturing technology prior to joining Tessera.