March 1998 - ChipScale Review

March 1998


eMail the Editor

A Key CSP Infrastructure Market

By Harvey S. Miller
Contributing Editor

The words chip-scale electronics convey more than simply a new semiconductor package. They represent a new infrastructure that's evolving as CSPs enter the mainstream.

PC board laminates, a $4 billion worldwide industry, are a chip-scale electronics infrastructure material facing dynamic change. CSP solder ball "leads" are flow soldered onto organic FR-4 laminate PC boards which dominate today's electronic interconnection.

Why are laminate choices exploding? Why are the new laminates so important to the mainstreaming process for chipscale electronics? The PC board laminate contributes to increased circuit performance and decreased equipment size.


As IC packages shrink to chip scale, the PC board traces interconnecting them must also be scaled down in every dimension.

We all know that performance dictates more efficient use of PC board space to attain shorter, finer lines, as logic ICs moved toward gigahertz speeds.

At the chip level, CSPs answer the challenge with single-chip modules which are easy-to-handle and easy-to-assemble with chip shooter equipment in place. And with low package parasitics, all in die-size formats, no wonder they are so appealing!

PC Board Challenges

CSPs and BGAs will challenge today's PC board interconnection density norms. But first, here's an example of how easy it will be to bring the over 40 billions of low leadcount IC devices into the chip-scale fold using standard laminate PC boards.

Last November, Information Storage Devices announced it's use of µBGA package for its latest voice storage multilevel EEPROM-60% smaller than the TSOP version.

That translates to a tiny 0.25 x 0.25 inch CSP to handle 17 leads in array (not inline) format with a pitch of 0.75 mm (30 mile). The company states there is "no problem with routing because of the low leadcount."

Moving on to other devices, DRAMs, SRAMs and flash memory are now going into chip-scale packages, boast lead counts of 40 and above.

For example, Intel's Flash Memory µBGA package (which is similar in size and pitch to ISD Devices) is 80% smaller than the TSOP version of the same device. The array is composed of 48 solder balls. The customer's board can be routed with 5 mil lines/spaces„within the production competence for most PC board makers.

But with lead counts increasing (to 100 for 64 Mb DRAMs) and lead pitches falling (to 0.5mm), board lines and spaces will have to move to 3 and 4 mils. Three resulting and corollary challenges to PC board laminates are to:

  1. Enable blind microvia-in-pad, finally replacing the space wasting dogbone offset through-hole,
  2. Improve intrinsic frequency enhancing characteristics and
  3. Offer increased stability.
In addition, as circuits become more dense, the uncompromised quality of their surfaces becomes more critical. All of these challenges and more are now being addressed by new laminate developments.


Figure 1„Compositech's copper clad laminate construction.

The laminates new bywords are cooler, flatter, smoother, stronger and thinner.

The Microvia Challenge

Via-in-pad is the dramatic space saver, which may be accomplished by laser, plasma or photo-definition technology. RCC (resin-coated copper) is a laminate enabler, available from Allied Signal. It contains no glass, so the two epoxy layers are easy to ablate after a copper window is etched. Under the copper, one layer is fully polymerized. The bonding layer is only B-staged (partially polymerized) to enable the flow and fill of circuit details by the resin. A typical construction might be 12 µm of low-tooth copper foil and 25 µm each for the two epoxy layers, both very uniform, providing a dielectric constant of 3.5.

Non-woven, epoxy-aramid paper from Arlon, DuPont and others is a laminate material which offers fast, easy processing for laser microvia formation. The aramid is copper-dad and epoxy impregnated. The aramid's CTE is half that of FR-4 and the dimensional stability is superior.

Other new laminate options include:

  • Copper-clad, adhesiveless polyimide film (available from Parlex and Sheldahl) is another option in new laminates.

  • Non-woven, parallel, flat glass filiments in Compositech's CL 200+. (These laminates remove all of the intrinsic sources of stress due to twisting yard and weaving fabric.)

  • Glasteel Industrial Laminates (GIL) and NELCO-Dielektra offer two continuous lamination processes which provide higher uniformity and freedom from dents.

Two developments among many breaking ones offering improved electrical characteristics are GE's PPO/epoxy GETEK, now second-sourced by MEM, and GIL's GML 1000 polyester laminate.

GETEK offers a combination of improved characteristics: 170 Tg, dielectric constant of 4 and a dissipation factor of .O1 at 1 MHz. GML 1000 compares favorably to PTFE in 10 GHz applications, with a dielectric constant of 3 from -55 to 80 °C and has a dissipation factor of .004 at 25°C.

The materials and improvements noted are only a very partial sample of the dynamism that's helping laminates meet the challenges of chip-scale electronics.

Harvey Miller is president of Kirk-Miller Associates, Palo Alto, CA. Contact him at 650.327.2029, fax 650.327.2360.



Chip Scale Review o 7291 Coronado Drive, Suite 8 o San Jose, CA 95129 o Email: editor@chipscalereview.com



Notes, 98/07/15, 05/13/99, ID=9803/editorial2
Keywords=bb00 fm00

© 1998 ChipScale REVIEW