Low-Cost, Chip-Sized Package Uses a Simple Substrate

Linda Jardine

David Francis

The construction details for this CSP package appear very simple: A substrate with a metallized pattern is bonded to a chip using adhesive polyimide tape. Connections between the chip and the traces on the substrate are made using Au or Al wire bonding. The completed assembly is then placed in a mold and encapsulated.

We assume the term "metal circuit substrate" means some type of printed wiring board as the phrase "circuit board" is used in the patent.

Two types of PWB designs are described and shown in the patent. The first contains a center slit so that memory devices with pads in the center of the chip can be bonded to the traces on the board.

A second type has a raised center portion and a lower perimeter portion. This design is for memory devices with perimeter pads. The raised portion of the substrate is the portion that contains the external pads. The lower portion contains the traces to which the wires are bonded.

No information is provided in the patent as to the amount of offset between the external pad level and the wire bond level of the substrate. Likewise, no information is given as to how the offset is formed in the substrate.

One possible approach for forming the substrate is to use a multilayer approach with a through-hole or a blind via to form the electrical connection between the wire bond trace and the external solder pad. Since the inventor claims the approach to be "low cost," this method is probably not the one used.

Another approach is to coin the single-layer PWB using heat and pressure. Normally, this method leaves some slope in the offset region, but this is not shown in any of the patent drawings. It may be that the draftsperson took the easy way out or there may be another method for making the substrate.

The metallization pattern on the substrate is very simple, and the external pad is a suitable size for solder reflow. An electrical trace connects this pad to the wire bond pad, which is shown to be the same width as the trace.

External pads are arranged in two rows, similar to a standard SO-type package. Nothing indicates that this design can be extended to pads in an area array pattern, but it could be if none of the traces crossed. The Tessera µBGA® patent is referenced as prior art.

The approach described in this patent is designed to extend the life of existing equipment and processes and is simple enough to be employed for other low leadcount devices.

Figure 1 - Molded CSP using a simple PWB.

International Interconnection Intelligence Inc. is a market and technology research company specializing in the semiconductor packaging and interconnection area. Contact the company at iii1@ix.netcom.com or 650.728.5270.