March 1998
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New Chip-Scale Package Technology Employs Chip-on-Flex and Laser Bonding
Using a flex-circuit interposer, researchers have developed a novel, low-cost way to fabricate a 645 micron-thick chip-scale package.By P. Kasulke of Pac Tech GmbH, Falkensee, Germany and G. Azdasht, E. Jung, E. Zakel and H. Reichl of the Fraunhofer Institute of Reliability and Microintegration (IZM), Berlin, Germany
The common technologies to mount ICs to substrates- either surface mount technology or chip-on-board- are being challenged by the increasing I/O density of current integrated circuits, by the drive to larger dies and by the user's desire to manufacture small, light-weight-but nonetheless highly reliable and cost effective devices.1,2
A new package must fit without major changes in current mass manufacturing processes, thus compatibility with the surface mount assembly process is required.
While there is a worldwide effort to allow the direct mounting of dies (flip-chip technology), several factors hinder this technology from entering mainstream applications. These include the availability of bumped known-good die (KGD) and possible changes in I/O distribution on the chip, due to shrunk or otherwise redesigned IC layouts. Additionally, handling issues on the customer side and cost considerations due to the necessary underfill are user concerns.
Chip-size/chip-scale package (CSPs) were designed to solve a majority of these issues. To overcome process constraints encountered with flip chips, interposers of ceramic or organic laminates-as well as polyimide films-are used to change a flip chip to a CSP, removing the necessity of an underfill step after assembly. 4,5
Most of the packaging techniques will allow a complete testing of the package, solving the KGD issue, and can easily cope with a changed I/O design. In the future, the customer can expect to receive a tested package with a standardized I/O layout. Unfortunately, however, the manufacturing of most of these CSPs are not cost competitive, compared to other packaging techniques. A strategy to realize distinctive lower costs is as follows:
- Design a package that requires only a few process and assembly steps.
- Select low-cost materials (copper laminates instead of gold conductors or thin film metallization).
- Design a production line that meets all the requirements for low-cost manufacturing.
The following details how these points can be combined to realize a high-performance and low-cost CSP. An additional feature of this package is its high reliability due to the encapsulation of the aluminum pads with electroless Ni/Au bumps.
Concept
The chip-size package presented here is based on the interconnection of the bare IC to a one-metal layer flexible interposer. Mechanical stability of the CSP is achieved by using a low stress, low-viscosity adhesive dispensed between chip and interposer before the connection is made. Solder balls for the CSP's attachment to the board were applied using a novel system for solder ball placement and controlled laser reflow, shown in Figure 1.As the first step, a 5 µm-thick Ni UBM (under bump metallization) is applied to the Al pads of the wafer. Besides the cost advantage of this maskless process, a very high uniformity of the layer and a near hermetic sealing of the Al pad is achieved. This guarantees a stable and highly reliable contact to the Al pads. To protect the Ni against oxidation and to achieve a high wettability, the Ni is covered with a thin gold flash. 6,7
Figure 1 - Production line flow chart.
Meniscus Soldering
Following the electroless Ni pretreatment a novel process is used to apply a thin ( 10 µm layer of AuSn20 solder to the nickel bumps. This is done also on the wafer level with a meniscus soldering machine. With this method, the wafer is brought in contact with a solder bath. The molten solder wets the Ni bumps, and when the wafer is removed, a small meniscus of solder is deposited on the bumps (Figures 2 and 3). A special technique is employed to prevent the oxidation of the solder bath or the solder deposits on the wafer.The cross sectioning in Figure 3 reveals that the deposition height of the solder is quite uniform and that a solder meniscus of about the same height was deposited on the nickel bump. Feasibility for fine pitch (70 µm and 100 µm) has been proven, as well. Besides being an attractive bumping process for a fluxless, chip-on-flex attachment method, this technique may serve as a low-cost replacement for electro-plated gold bumps for TAB technology.
Due to the special design of the solder reservoir, the input of solder may be reduced to a minimum. For example, approximately 50 g (0.05 kg) of molten solder is enough for a reliable attachment to the I/Os on the wafer. The meniscus soldering machine is capable of a throughput of 20 wafers/hour, sufficient for a production environment. This process is also suitable for different soft- solder alloys or metals like eutectic AuSn, PbSn alloys, tin and indium. The metallization on the wafer is either electroless grown nickel, galvanic gold or gold bumps
The Flexible Interposer
A three-layer (one-metal layer) tape was selected to keep the costs of the interposer as low as possible. This tape consists of a rolled copper layer (20 µm), which is laminated using an adhesive ( 15 µm) to the polymer film (50 µm). Following lamination, the adhesive is cured. The lead pattern is then photolithographically defined and etched. Subsequently, the pattern is plated with a thin gold layer (0.2 - 0.5 µm) or electroless tin (0.5 µm).Since ICs with peripheral pitches of 200 µm currently need to be redistributed to an area-array configuration of 500-800 µm pitch, a fine-line technology was used ( 100 µm lines and spaces), combining fanning in and fanning out of the contacts. The overall size of the CSP is therefore only approximately 1 mm larger in the x and y directions for a 10x10 mm2 IC. Figure 4 shows a fan-in/fan-out configuration for a die with 184 I/Os.
Due to the interconnection technology employed, a window opening for bonding in the inner lead area, which is commonly used for bonding with a thermode, is not needed.
Figure 2 - A row of nickel bumps after meniscus soldering using eutectic AuSn is shown. | 
Figure 3 - Cross-section through Ni bumps with AuSn20. | 
Figure 4 - Redistribution of the contacts on the flex cirsuit interposer. |
The advantage of eliminating this window opening is a cost reduction in manufacturing and a higher stability of the interposer. Another feature is a simplified assembly, because the entire circuit pattern is covered by the polymer film, and openings at the pad positions allow the deposition of bumps by solder ball placement.
Figure 5 - I/O has been interconnected between the chip and flex interposer using the FPC method. | 
Figure 6 - Flex circuit interposer with bumps. | 
Figure 7 - Flex interposer with deposit solder balls is shown. |
Connecting to the Interposer
For interconnecting the chip to the flex substrate, a Laser-FPC (fiber-push-connection) bonder, similar to a wire bonder, is used. The principle of the FPC method was described in detail by Azdasht et al 8,9For the bond tool, a highly stable glass fiber (220 µm diameter) was used. While the glass fiber maintains the applied bond force, a laser pulse is transported through the glass fiber, heating the contact zone. The heat generated within the contact zone leads to the emission of IR radiation, which is guided back through the fiber to an IR detector. The detector sends feedback to the laser temperature control unit, enabling precise temperature control during bonding.
The great advantage of the FPC method is the capability of bonding through the polymer film. The laser beam passes through the polymer directly onto the copper leads and is transformed into thermal energy. This is possible due to the low adsorption property of the flex at the wavelength (I = 1064 nm) of the Nd:YAG laser used. During laser pulsing, the temperature control avoids damaging the polymer and adhesive layers.
Since the electrical interconnection must be established and mechanical stability must be provided for an SMT-compatible pick-and-place procedure, a low viscosity, low stress adhesive is dispensed before the interconnection. The subsequent cure (90 °C) is performed during the interconnection of the
I/Os of the chip to the flex interposer (Figure 5) on the hotplate of the bonder. No interference of the adhesive material with the interconnection process was observed due to the nature of the FPC technology.
Figure 6 shows the circuit side of the interposer after interconnection. The chip was not underfilled and the Al under the nickel bump was selectively removed by an Al etching process. The laser parameters are a power of 5 Watts and a pulse width of 10 ms with an applied bond force of 40 cN. The achieved solder meniscus between bump and lead guarantees a high connection stability.
The laser FPC bonder was initially designed for TAB applications, but was adapted for the flexible interposer. Using glass fibers with copper coating, bond forces up to 800 cN (with a glass fiber diameter of 300 µm) can be realized. This semiautomatic reel-to-reel bonder, with a bond speed of 15 bonds/sec, was developed in cooperation with F&K Delvotec. A fully automatic production bonder is under development.
CSP Solder Ball Attachment
The CSP is provided with solder balls to allow reel-to-reel processing. These solder balls are placed on the CSP with a highspeed solder ball bumper (SBB). The SBB's operating principal is based on the placement and controlled laser reflow of pre-formed solder balls in one step10.The solder balls can be of any desired alloy with a welldefined size. The process does not require any masking, micro-machined forms nor micro-puncture technology; nor is flux or a second reflow needed for the ball attach. Due to the small input of thermal energy during solder ball attach, damage to the flex interposer is avoided. During laser reflow, nitrogen acts as a shielding atmosphere and allows the solder ball to reflow to a smooth, hemispherical bump on the pad.
Figure 7 shows the flexible interposer with solder balls (30O µm 63/37 PbSn) attached to the CSP. Various types of CSPs can be processed due to the data-driven, ball-placement capability.
The entire package is 645 µm thick, including a 550 µmthick chip and a 85 µm-thick tape carrier. Figure 8 shows a cross section of the prototype package.
Reliability Testing
Reliability is a very important aspect for the wide acceptance of a CSP, and a minimum of 1000 thermal cycles may be required, typical of the test methods defined in Mil-Std-883. As a first step, the intrinsic reliability of the package was tested. Packages were subjected to thermal cycles between -55 and 125°C, and CSPs with and without adhesive underfill were subjected to the tests for comparison. The metallurgy before and after the thermal cycling was investigated by BSE so that intermetallics could be detected.A solder-joints on the assembly after 1000 thermal cycles did not show any degradation or failure. At the interface between eutectic solder and Ni, Ni3Sn2 intermetallic forms during bumping and continues to grow during bonding and storage. Earlier investigations showed that this intermetallic does not affect the reliability of the assembly. At the interface to the copper lead, a thin layer of copper/gold forms during the bonding process. This phase does not lead to a degradation of the solder joint either, and therefore has no impact on the reliability of the package.
Further reliability and lifetime investigations of these CSPs are a focus of our ongoing research efforts and will be published at a later date.
Figure 8 - Cross-section of the prototype CSP.
Summary
A CSP was developed from the conceptual approach to final realization. Emphasis was placed on the use of low-cost mate rials and low-cost processes as well as on high flexibility. The process goals were achieved with the IC pre-treatment using electroless nickel and covering this UBM with AuSn20 solder.A laser FPC bonder was used for interconnections. High speed solder ball placement was employed to deposit the required amount of solder to the flexible interposer's pads. The CSP obtained is fully surface-mount compatible, allowing a wide process window.
References
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- A. Ostmann, J. Simon and H. Reichl, "The Pretreatment of A1 Bondpads for Electroless Nickel Bumping," Proc. IEEE MCM Conf. 93, Santa Cruz, CA.
- A. Ostmann, et al., "Low Cost Techniques for Flip Chip Soldering," in Proc. SMI Conf. 96, San Jose.
- G. Azdasht, E. Zakel and H. Reichl, "A New ChipPackaging Method using Windowless FlipTAB Laser Connection on Flex Circuits," Proc. ITAP 95, San Jose, 237-242.
- G. Azdasht, P. Kasulke, E. Zakel and H. Reichl, "The Use of the FPC-Laser Method for Different Chip Interconnection Techniques," Proc. IEMT Symposium 95, Omiya, Japan, 397-402.
- P. Kasulke,et al., "Solder Ball Bumper (SBB)-A Flexible Equipment for FC, CSP, BGA and Printed Circuit Boards," Proc. ITAP 97, Sunnyvale, 38-43.
(This article is based on a paper presented at the Second International Conference on Chip Scale Packaging (CHIPCON '97), Feb. 21 -22, 1997, Sunnyvale, CA and, reprinted with permission. ©Copyright 1997 by the Semiconductor Technology Center Inc.,P.O. Box 38, Neffs, PA 18065. All rights reserved.)